WO2002103755A9 - Semiconductor die including conductive columns - Google Patents
Semiconductor die including conductive columnsInfo
- Publication number
- WO2002103755A9 WO2002103755A9 PCT/US2002/019073 US0219073W WO02103755A9 WO 2002103755 A9 WO2002103755 A9 WO 2002103755A9 US 0219073 W US0219073 W US 0219073W WO 02103755 A9 WO02103755 A9 WO 02103755A9
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- conductive
- aperture
- solder
- layer
- column
- Prior art date
Links
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Definitions
- a silicon die is joined to a ceramic substrate carrier.
- the ceramic substrate carrier with the die is mounted on an organic board.
- a passivation layer is formed on a semiconductor die (which may be in a semiconductor wafer).
- the passivation layer includes apertures that expose metal regions on the semiconductor die. Titanium and copper layers are sputtered on the upper surface of the conductive regions and the passivation layer.
- a layer of photoresist is then patterned on the semiconductor die so that the apertures in the patterned photoresist layer are over the conductive regions. Solder is electroplated in the apertures in the photoresist layer until the apertures are filled with solder. The photoresist is stripped and the portions of the titanium and copper layers around the solder deposits are removed. Then, the solder deposits are subjected to a full reflow process.
- the full reflow process causes the solder deposits to form solder balls.
- the semiconductor die is bonded face-down to a carrier.
- the solder balls on the semiconductor die contact conductive regions on the chip carrier.
- Non-soluble barriers are disposed around the conductive regions and constrain the solder balls.
- the solder balls between the conductive regions on the carrier and the semiconductor die melt and wet the conductive regions on the carrier. Surface tension prevents the melting solder from completely collapsing and holds the semiconductor die suspended above the carrier.
- the deposited solder substantially deforms into solder balls. Because of the deformation, the heights of the resulting solder balls on the semiconductor die can be uneven. If the heights of the solder balls are uneven, the solder balls may not all contact the conductive regions of the carrier simultaneously when the semiconductor die is mounted to the chip carrier. If this happens, the strength of the formed solder joints may be weak thus potentially decreasing the reliability of the formed package. Also, the area of contact between the conductive regions and the solder balls are small, because the areas at the tips of the solder balls are small.
- Embodiments of the invention address these and other problems.
- Embodiments of the invention include semiconductor die packages and methods for forming semiconductor die packages.
- One embodiment of the invention is directed to a method for forming a semiconductor die package, the method comprising: a) providing a mask having an aperture on a semiconductor substrate, wherein a conductive region is on the semiconductor substrate and the aperture in the mask is disposed over the conductive region; b) placing a pre-formed conductive column witfiin the aperture; and c) bonding the pre-formed conductive column to the conductive region, wherein the pre-formed conductive column has substantially the same shape before and after bonding.
- a method for forming a semiconductor die package comprising: a) forming a passivation layer comprising a first aperture on a semiconductor substrate comprising a conductive region, wherein the aperture in the mask is disposed over the conductive region; b) forming an adhesion layer on the passivation layer and on the conductive region; c) forming a seed layer on the adhesion layer; d) forming a patterned photoresist layer comprising a second aperture on the passivation layer, wherein the second aperture is over the conductive region and is aligned with the first aperture; e) electroplating a conductive layer within the second aperture and on the seed layer; f) depositing solder paste containing a flux within the second aperture and on the electroplated conductive layer; g) inserting a pre-formed conductive column into the second aperture; h) placing the pre-formed conductive column on the conductive layer within the second aperture; i) removing the patterned photoresist layer; j) etching
- Another embodiment of the invention is directed to a method for forming a semiconductor die package, the method comprising: a) forming a mask comprising an aperture disposed over a conductive region on a semiconductor substrate, wherein the aperture is disposed over the conductive region; b) plating a conductive column within the second aperture and on the conductive region; and c) removing the mask from the semiconductor substrate.
- Another embodiment of the invention is directed to a semiconductor die package comprising: a) a semiconductor die; b) a conductive region on the semiconductor substrate; c) a passivation layer comprising an aperture on the semiconductor substrate, wherein the aperture is disposed over the conductive region; and d) a pre-formed, conductive column comprising a lead-free, conductive columnar body and a coating on a conductive columnar body.
- FIGS. 1(a) through l(i) show simplified cross-sections of semiconductor substrates as they are processed according to an embodiment of the invention.
- FIGS. 2(a) through 2(c) show simplified cross-sections of semiconductor substrates as they are processed according to another embodiment of the invention.
- FIGS. 3(a) and 3(b) show simplified cross-sections of semiconductor substrates as they are processed in another embodiment of the invention.
- FIG.4 shows a cross-section of a vertical MOSFET device.
- FIG. 5 shows the underside of a semiconductor die with the pre-formed conductive columns.
- Embodiments of the invention are directed to methods for forming semiconductor die packages.
- a mask having an aperture is provided on a semiconductor substrate.
- the mask may be formed on the semiconductor substrate.
- the mask may be a photoresist layer that is patterned on the semiconductor substrate.
- the mask may be pre-formed.
- a mesh mask with apertures can be formed. Then, an aperture in the mesh mask can be aligned with the conductive region on the semiconductor substrate.
- the aperture in the mask is disposed over the conductive region and exposes the conductive region.
- a pre-formed conductive column is then placed within the aperture and is bonded to the conductive region.
- the mask may then be removed from the semiconductor substrate.
- the semiconductor substrate can be diced to form individual dies. After dicing, the individual dies can be mounted on die carriers, lead frames, circuit substrates, etc.
- the pre-formed conductive column can be bonded to the conductive region without perfo ⁇ ning a full reflow process.
- less time and/or less heat is needed to form an interconnect on a semiconductor substrate than the conventional solder ball formation process described above.
- Reducing the heating temperature and/or the heating time associated with forming an interconnect on a semiconductor substrate has a number of advantages. For example, by reducing the processing time and processing temperature, processing costs are reduced as less energy and time are needed to make the die package.
- the likelihood that intermetallics will form in the interconnects is reduced or eliminated. This results in less brittle, and stronger interconnects and consequently a more reliable die package.
- the conductive columns do not substantially deform like fully reflowed solder deposits. Consequently, the ends of the conductive columns are substantially coplanar. Good electrical contact can be made between the ends of the conductive columns and the conductive regions to which the ends are attached.
- FIG. 1(a) shows a structure comprising a semiconductor substrate 10 and a conductive region 12 on the semiconductor substrate 10.
- the conductive region 12 may be in any suitable form.
- the conductive region 12 may be a circular or rectangular pad, or conductive line.
- the conductive region 12 can comprise any suitable conductive material.
- the conductive region 12 may comprise a metal such as aluminum, copper, nickel, gold, etc.
- a passivation layer 14 is on the semiconductor substrate 10.
- the passivation layer 14 includes a first aperture 25 that is positioned over and exposes the conductive region 12.
- Any suitable material may be used to form the passivation layer 14.
- Such materials may include, for example, silicon nitride, glass, or polymeric materials such as polyimide.
- the semiconductor substrate 10 can include one or more semiconductor dies.
- a semiconductor substrate is a silicon wafer that includes a plurality of semiconductor dies. The semiconductor dies may be separated from each other after the pre-formed conductive columns are bonded to each of the semiconductor dies in the semiconductor substrate 10. Any suitable semiconductor material including silicon, gallium arsenide, etc. can be used in the semiconductor substrate 10.
- the semiconductor substrate 10 and the one or more dies in the semiconductor substrate 10 may include any suitable active or passive semiconductor device.
- the semiconductor substrate 10 may comprise a metal oxide field effect transistor (MOSFET) device such as a power MOSFET device.
- MOSFET metal oxide field effect transistor
- the MOSFET device may have planar or trenched gate structures. Trenched gate structures are preferred. Transistor cells containing trenched gate structures are narrower than planar gate structures.
- the MOSFET device may be a vertical MOSFET device. In a vertical MOSFET device, the source region and the drain region are at opposite sides of the semiconductor die so that current in the transistor flows vertically through the semiconductor die. A cross-section of a typical vertical MOSFET device is shown in FIG. 4. FIG. 1(a) and other figures are simplified for purposes of illustration.
- FIG. 1(a) shows one aperture in the passivation layer 14.
- many conductive regions may be on the semiconductor substrate 10 and many apertures may be in the passivation layer 14 in embodiments of the invention. Consequently, many conductive columns can be bonded to the semiconductor substrate 10.
- an underlayer 16 of material can be deposited on the conductive region 12.
- the underlayer 16 can comprise any suitable number of sublayers.
- the underlayer 16 may comprise one or more metallic sublayers.
- the metallic sublayers may comprise an adhesion layer, a diffusion barrier, a solder wettable layer, and an oxidation barrier layer.
- the underlayer 16 may comprise a refractory metal or metal alloy layer such as a titanium (Ti) layer or titanium tungsten (TiW) layer.
- the underlayer 16 may also include a copper seed layer.
- the titanium layer or the titanium tungsten (TiW) layer may be used to adhere the copper seed layer to the conductive region 12, while the copper seed layer can be used to initiate a plating process.
- the underlayer 16 and any sublayers thereof can be deposited on the semiconductor substrate 10 using any suitable method.
- the layers may be deposited on the semiconductor substrate 10 by processes such as sputtering, electroless plating, or evaporation.
- a Ti or TiW layer having a thickness in the range of about 0.1 to about 0.2 micron can be sputtered over the entire surface of the passivation layer 14 and the conductive region 12 exposed through the passivation layer 14.
- a copper or copper alloy layer of about 0.3 to about 0.8 microns can be sputtered on the Ti or TiW layer.
- a continuous photoresist layer 18 is deposited on the semiconductor substrate 10.
- a photolithography process can then be used to pattern the photoresist layer 18.
- the photoresist layer 18 can be irradiated and then developed to form a mask 28.
- the mask 28 can include a second aperture 20.
- the second aperture 20 exposes a portion of the underlayer 16 and is positioned above the conductive region 12. Positive or negative photoresist materials may be used to form the mask 28.
- a copper layer 22 is deposited within the second aperture 20 and on the underlayer 16.
- the copper layer 22 may comprise copper or a copper alloy, and can be deposited on the underlayer 16 using any suitable process.
- the copper layer 22 can be formed by electroplating.
- the thickness of the formed copper layer can be from about 10 to about 30 microns in some embodiments.
- copper is mentioned in this example, any suitable conductive material can be used instead of copper.
- the copper layer 22 could alternatively be a gold layer or a nickel layer.
- solder paste 24 is deposited within the second aperture 20.
- the solder paste 24 can comprise a carrier, a flux material, and metallic solder alloy particles.
- the solder paste 24 can be in the form of a layer with any suitable thickness. In some embodiments, the solder paste 24 can have a thickness less than a few microns (e.g., less than about 50 microns).
- the solder particles in the solder paste 24 may include any suitable material.
- Exemplary solder materials may comprise PbSn, InSb, etc. in any suitable weight or atomic proportions.
- the solder particles can comprise a standard eutectic solder composition (e.g., 63/37 PbSn).
- any suitable flux material can be used in the solder paste.
- a rosin flux could be used. Rosin fluxes promote wetting of the metal surfaces by chemically reacting with oxide layers on the surfaces. After fluxing, oxide-free surfaces can readily wet with, for example, the melting solder.
- tin and lead oxides on PbSn solder particles can be removed using a rosin flux. Copper oxide on a copper pad can also be removed using a rosin flux. The melting solder particles can then contact and wet the oxide-free copper pad.
- a pre-formed conductive column 30, 31, 35 is then inserted into the second aperture 20 in the mask 28.
- the pre-formed conductive column 30 contacts the solder paste 24 within the second aperture 20 and is immobilized on the solder paste 24.
- a conductive adhesive layer could be used to bond the conductive column to the copper layer 22 and the conductive region 12.
- the pre-formed conductive columns 30, 31, 35 can be in any suitable form.
- the pre-formed conductive columns can have any suitable aspect ratio, where the aspect ratio can be defined as the longest cross-sectional length divided by the smallest cross-sectional width.
- the aspect ratio could be, e.g., greater than about 0.5 (e.g., about 1-2). Higher aspect ratio columns are desirable as they reduce the shear stress caused by mismatches between the coefficients of thermal expansion (CTEs) of the semiconductor die and a die carrier upon which the semiconductor die is mounted.
- the radial cross- sections of the columns can be circular, polygonal, etc.
- the preformed conductive columns 30, 31, 35 can be cylinders or parallelepipeds such as cubes.
- the pre-formed conductive columns may have a head and a stem so that the column has a mushroom-like shape. Before and after the conductive column 30, 31, 35 is bonded to the conductive region 12, the side walls of the conductive column 30, 31, 35 are substantially parallel to each other (unlike a solder ball).
- One conductive column 30 can comprise a high lead (Pb) solder.
- a typical high lead solder can have a lead content that is greater than 63 percent by weight.
- the high lead solder can comprise, for example, 95/5 PbSn or 90/10 PbSn (% by weight).
- a conductive column comprising a high lead solder can have a higher melting point than, for example, a eutectic solder composition (e.g., 63/37 PbSn).
- solder paste 24 under the conductive column 30 comprises solder particles made of a standard eutectic solder
- the solder paste 24 can be heated between the melting temperatures of the eutectic solder and the high lead solder.
- the eutectic solder in the solder paste 24 can melt and bond the conductive column 30 to the conductive region 12 without melting the conductive column 30.
- the conductive column 30 retains its shape and the heights of the conductive columns that are bonded to the semiconductor substrate 10 are substantially co-planar.
- Another conductive column 31 shown in FIG. 1(g) comprises a conductive columnar body 32 and a coating 33 on the conductive columnar body 32.
- the conductive columnar body 33 and/or the coating 33 are lead-free. Reducing the amount of lead in the formed package makes the package more environmentally friendly.
- the coating 33 can be present on the top and bottom, and even on the sides of the conductive columnar body 32.
- the conductive columnar body 32 can comprise any suitable conductive material. Suitable conductive materials include copper, alurninum, and noble metals such as gold, silver, and alloys thereof.
- the coating 33 on the conductive columnar body 32 can include one or more layers of material. The one or more layers may include any suitable metallic layers.
- the metallic layers may include, for example, one or more of barrier layers, adhesion layers, diffusion barriers, and solder wettable layers. Layers such as these are sometimes referred to as "underbump metallurgy layers". Nickel and gold layers are two specific examples of metallic layers that can be on the columnar bodies.
- a conductive column 35 having a head 35(a) and a stem 35(b) is also shown in FIG. 1(g).
- the conductive column has a mushroom-like shape.
- the stem 35(b) can be inserted into the aperture 20 and can contact the solder paste 24 while the head 35(a) can remain above the mask 28.
- the conductive column 35 could comprise a high-lead solder.
- the conductive column 35 may comprise a columnar body comprising, for example, copper and a coating on one, some, or all sides of the columnar body.
- the coating may include one or more of the previously described metallic layers.
- the pre-formed conductive columns used in embodiments of the invention may be formed in any suitable manner.
- a long conductor may be formed by an extrusion process.
- the long conductor may then be cut to form individual columnar bodies.
- the formed columnar bodies can then be optionally coated with any suitable material.
- columnar bodies can be plated with solder or one or more metallic layers.
- Each pre-formed conductive column can comprise a columnar body and a layer of material (e.g., solder) on it.
- the long conductor may first be coated and then cut.
- the pre-formed conductive columns or the columnar bodies can be molded in a suitable mold.
- the mask 28 can be removed.
- the mask 28 can be removed using, for example, a standard stripping process.
- the regions of the underlayer 16 around the conductive column 30 can be removed.
- the region of the underlayer 16 around the conductive column 30 can be removed using a brief etch. For example, these regions can be etched using a stripping solution of hydrogen peroxide. The brief etch process does not remove a substantial amount of the conductive column 30 so that the conductive column 30 remains on the semiconductor substrate 10 after the brief etch.
- heat can be applied to solder paste 24 to form a solder joint 35.
- Flux in the solder paste 24 reacts with and removes oxides from the surfaces of the solder particles and the surfaces of the conductive column 30 and the copper layer 22.
- the solder particles in the solder paste 24 melt and solidify to form a complete solder joint 35.
- the amount of heat and the duration of heat that is applied to the solder joint 35 is less than the amount of heat and the heating time that is used to perform a full reflow process.
- only the solder particles in the solder paste 24 need to melt to form a solder joint.
- the pre-formed conductive column 30 does not deform in an appreciable manner. Less time and less energy is needed to form an interconnect such as the conductive column 30 on the semiconductor substrate 10 in comparison to a conventional solder ball process.
- any flux residue remaining around the solder joint 35 can be removed using conventional flux removal processes. If the semiconductor substrate 10 includes a plurality of semiconductor dies, the semiconductor substrate 10 can be diced. After dicing, individual semiconductor dies can be mounted on die carriers.
- Embodiments of the invention are not limited to the particular order of process steps described above.
- the solder paste 24 can be heated to form a solder joint 35 before the mask 28 is removed.
- the underlayer 16 could be deposited on the conductive region 12 after the mask 28 is formed.
- FIGS. 2(a) to 2(c) Other embodiments of the invention can be described with reference to FIGS. 2(a) to 2(c).
- the processing steps that are described with respect to FIGS. 1(a) to 1(e) can first be performed.
- a flux composition 39 i.e., with or without solder particles
- the deposited flux composition 39 is in contact with the copper layer 22. It can include any of the previously described flux materials.
- a pre-formed conductive column 41 can be placed on the flux composition 39.
- the pre-formed conductive column 41 comprises a columnar body 42 and a solder coating 43 on the columnar body 42.
- the columnar body 42 can comprise a metal such as copper or gold.
- the columnar body 42 is lead-free and has a high melting temperature (e.g., greater than 500 °C).
- the solder in the solder coating 43 on the columnar body 42 has a lower melting temperature than the metal in the columnar body 42.
- the solder coating 43 can be on the top and the bottom, as well as on one or more of the sides of the columnar body 42.
- the pre-formed conductive column 41 could also have one or more of the previously described metallic layers (not shown) between the columnar body 42 and the solder coating 43.
- the pre-formed conductive column 41 shown in FIG.2(b) can be formed in any suitable manner.
- a long conductor may be formed by an extrusion process.
- the long conductor can then be optionally coated with solder using, for example, an electroplating process or a pultrusion process.
- the long conductor having- a rectangular or square cross-section can be pulled through a hole in a die.
- the hole has a larger cross-sectional area than the cross-sectional area of the long conductor.
- solder on one side of the die can coat the long conductor as it is pulled through the hole.
- the solder coated conductor can be cut to form individual, pre-formed columns.
- These pre-formed conductive columns can be mounted on conductive regions on a semiconductor substrate.
- Each conductive column includes a solder coating and an inner columnar body of metal.
- the pre-formed conductive column 41 can then be heated so that the flux composition 39 and the portion of the solder coating 43 that contacts the flux composition 39 mix.
- solder joint 44 binds the columnar body 42 to the conductive region.
- the mask 28 and the regions of the underlayer 16 around the solder joint 44 can be removed in the same or different manner as described above.
- a pre-formed conductive column including a solder coated columnar body has a number of advantages.
- the amount of lead (Pb) that is used in the pre-formed conductive column 41 is less than in an interconnect that is made of all solder (e.g., as in a solder ball).
- die packages that are made using the pre-formed conductive column 41 are more environmentally friendly than conventional solder ball-type die packages.
- the conductive column that is formed on the conductive region on the semiconductor substrate need not be pre-formed.
- a conductive column can be formed on a conductive region of a semiconductor substrate by a process such as electroplating or electroless plating.
- the processing steps that are shown in FIGS. 1(a) to 1(d) and that are described above with respect to FIGS. 1(a) to 1(d) can be performed.
- plating continues so that a conductive column 48 is formed in the aperture 20 in the mask 28.
- the conductive column 48 can be formed by a plating process such as electroplating or electroless plating.
- copper is preferably used in the conductive column 48, other materials such as nickel or gold can be in the conductive column 48.
- the mask 28 is then removed leaving a free-standing conductive column 48 on the semiconductor substrate 10. After removing the mask 28, regions of the underlayer 16 around the conductive column 48 can be removed in the same or different manner as described above. Then, the semiconductor substrate can be diced and the individual dies with the conductive columns can be mounted to, for example, die carriers.
- the conductive column 48 is lead-free.
- the amount of lead in the formed package is reduced in comparison to many conventional packages, thus making the formed package more environmentally friendly than many conventional packages.
- FIG. 5 shows the underside of a semiconductor die 105 with a plurality of conductive columns 120-1, 120-2 on it.
- conductive columns with different cross-sectional geometries.
- cylindrical conductive columns 120-1 can be coupled to the source regions of a vertical MOSFET device in the semiconductor die 105.
- a cubic conductive column 120-2 is at one corner of the semiconductor die 10 and can be coupled to the gate region of the MOSFET.
- the illustrated embodiment can be flipped over and then mounted to a die carrier, lead frame, circuit substrate, etc.
Abstract
Description
Claims
Priority Applications (1)
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AU2002322116A AU2002322116A1 (en) | 2001-06-15 | 2002-06-13 | Semiconductor die including conductive columns |
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US09/881,787 | 2001-06-15 | ||
US09/881,787 US6683375B2 (en) | 2001-06-15 | 2001-06-15 | Semiconductor die including conductive columns |
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WO2002103755A2 WO2002103755A2 (en) | 2002-12-27 |
WO2002103755A3 WO2002103755A3 (en) | 2003-04-03 |
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US (2) | US6683375B2 (en) |
AU (1) | AU2002322116A1 (en) |
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Families Citing this family (90)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6720642B1 (en) * | 1999-12-16 | 2004-04-13 | Fairchild Semiconductor Corporation | Flip chip in leaded molded package and method of manufacture thereof |
US6870254B1 (en) | 2000-04-13 | 2005-03-22 | Fairchild Semiconductor Corporation | Flip clip attach and copper clip attach on MOSFET device |
US6661082B1 (en) * | 2000-07-19 | 2003-12-09 | Fairchild Semiconductor Corporation | Flip chip substrate design |
US6753605B2 (en) * | 2000-12-04 | 2004-06-22 | Fairchild Semiconductor Corporation | Passivation scheme for bumped wafers |
US6798044B2 (en) * | 2000-12-04 | 2004-09-28 | Fairchild Semiconductor Corporation | Flip chip in leaded molded package with two dies |
US6469384B2 (en) * | 2001-02-01 | 2002-10-22 | Fairchild Semiconductor Corporation | Unmolded package for a semiconductor device |
US6853076B2 (en) * | 2001-09-21 | 2005-02-08 | Intel Corporation | Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same |
US6891256B2 (en) | 2001-10-22 | 2005-05-10 | Fairchild Semiconductor Corporation | Thin, thermally enhanced flip chip in a leaded molded package |
JP3829325B2 (en) * | 2002-02-07 | 2006-10-04 | 日本電気株式会社 | Semiconductor element, manufacturing method thereof, and manufacturing method of semiconductor device |
US7122884B2 (en) * | 2002-04-16 | 2006-10-17 | Fairchild Semiconductor Corporation | Robust leaded molded packages and methods for forming the same |
US20040007779A1 (en) * | 2002-07-15 | 2004-01-15 | Diane Arbuthnot | Wafer-level method for fine-pitch, high aspect ratio chip interconnect |
JP3944026B2 (en) * | 2002-08-28 | 2007-07-11 | キヤノン株式会社 | Envelope and manufacturing method thereof |
US6892925B2 (en) * | 2002-09-18 | 2005-05-17 | International Business Machines Corporation | Solder hierarchy for lead free solder joint |
US6854636B2 (en) * | 2002-12-06 | 2005-02-15 | International Business Machines Corporation | Structure and method for lead free solder electronic package interconnections |
US7217594B2 (en) * | 2003-02-11 | 2007-05-15 | Fairchild Semiconductor Corporation | Alternative flip chip in leaded molded package design and method for manufacture |
US6867481B2 (en) * | 2003-04-11 | 2005-03-15 | Fairchild Semiconductor Corporation | Lead frame structure with aperture or groove for flip chip in a leaded molded package |
US6917113B2 (en) * | 2003-04-24 | 2005-07-12 | International Business Machines Corporatiion | Lead-free alloys for column/ball grid arrays, organic interposers and passive component assembly |
US6927493B2 (en) * | 2003-10-03 | 2005-08-09 | Texas Instruments Incorporated | Sealing and protecting integrated circuit bonding pads |
US7196313B2 (en) * | 2004-04-02 | 2007-03-27 | Fairchild Semiconductor Corporation | Surface mount multi-channel optocoupler |
US7678680B2 (en) * | 2004-06-03 | 2010-03-16 | International Rectifier Corporation | Semiconductor device with reduced contact resistance |
TWI313051B (en) * | 2004-06-10 | 2009-08-01 | Advanced Semiconductor Eng | Method and structure to enhance height of solder ball |
US7256479B2 (en) * | 2005-01-13 | 2007-08-14 | Fairchild Semiconductor Corporation | Method to manufacture a universal footprint for a package with exposed chip |
KR101298225B1 (en) * | 2005-06-30 | 2013-08-27 | 페어차일드 세미컨덕터 코포레이션 | Semiconductor die package and method for making the same |
US7285849B2 (en) * | 2005-11-18 | 2007-10-23 | Fairchild Semiconductor Corporation | Semiconductor die package using leadframe and clip and method of manufacturing |
US20090057852A1 (en) * | 2007-08-27 | 2009-03-05 | Madrid Ruben P | Thermally enhanced thin semiconductor package |
US7371616B2 (en) * | 2006-01-05 | 2008-05-13 | Fairchild Semiconductor Corporation | Clipless and wireless semiconductor die package and method for making the same |
US20070164428A1 (en) * | 2006-01-18 | 2007-07-19 | Alan Elbanhawy | High power module with open frame package |
US7868432B2 (en) * | 2006-02-13 | 2011-01-11 | Fairchild Semiconductor Corporation | Multi-chip module for battery power control |
US20070231475A1 (en) * | 2006-03-31 | 2007-10-04 | Tadanori Shimoto | Conductor structure on dielectric material |
US7768075B2 (en) * | 2006-04-06 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die packages using thin dies and metal substrates |
US7618896B2 (en) | 2006-04-24 | 2009-11-17 | Fairchild Semiconductor Corporation | Semiconductor die package including multiple dies and a common node structure |
US7541681B2 (en) * | 2006-05-04 | 2009-06-02 | Infineon Technologies Ag | Interconnection structure, electronic component and method of manufacturing the same |
US7476978B2 (en) * | 2006-05-17 | 2009-01-13 | Infineon Technologies, Ag | Electronic component having a semiconductor power device |
US7757392B2 (en) | 2006-05-17 | 2010-07-20 | Infineon Technologies Ag | Method of producing an electronic component |
US7626262B2 (en) * | 2006-06-14 | 2009-12-01 | Infineon Technologies Ag | Electrically conductive connection, electronic component and method for their production |
US7656024B2 (en) * | 2006-06-30 | 2010-02-02 | Fairchild Semiconductor Corporation | Chip module for complete power train |
US7564124B2 (en) * | 2006-08-29 | 2009-07-21 | Fairchild Semiconductor Corporation | Semiconductor die package including stacked dice and heat sink structures |
US7768105B2 (en) * | 2007-01-24 | 2010-08-03 | Fairchild Semiconductor Corporation | Pre-molded clip structure |
US8106501B2 (en) * | 2008-12-12 | 2012-01-31 | Fairchild Semiconductor Corporation | Semiconductor die package including low stress configuration |
US7821116B2 (en) * | 2007-02-05 | 2010-10-26 | Fairchild Semiconductor Corporation | Semiconductor die package including leadframe with die attach pad with folded edge |
KR101391925B1 (en) * | 2007-02-28 | 2014-05-07 | 페어차일드코리아반도체 주식회사 | Semiconductor package and semiconductor package mold for fabricating the same |
KR101489325B1 (en) * | 2007-03-12 | 2015-02-06 | 페어차일드코리아반도체 주식회사 | Power module with stacked flip-chip and method of fabricating the same power module |
US7659531B2 (en) * | 2007-04-13 | 2010-02-09 | Fairchild Semiconductor Corporation | Optical coupler package |
US7683463B2 (en) * | 2007-04-19 | 2010-03-23 | Fairchild Semiconductor Corporation | Etched leadframe structure including recesses |
US20090008430A1 (en) * | 2007-07-06 | 2009-01-08 | Lucent Technologies Inc. | Solder-bonding process |
US7902657B2 (en) * | 2007-08-28 | 2011-03-08 | Fairchild Semiconductor Corporation | Self locking and aligning clip structure for semiconductor die package |
US7737548B2 (en) | 2007-08-29 | 2010-06-15 | Fairchild Semiconductor Corporation | Semiconductor die package including heat sinks |
US20090057855A1 (en) * | 2007-08-30 | 2009-03-05 | Maria Clemens Quinones | Semiconductor die package including stand off structures |
US7589338B2 (en) * | 2007-11-30 | 2009-09-15 | Fairchild Semiconductor Corporation | Semiconductor die packages suitable for optoelectronic applications having clip attach structures for angled mounting of dice |
US20090140266A1 (en) * | 2007-11-30 | 2009-06-04 | Yong Liu | Package including oriented devices |
KR20090062612A (en) * | 2007-12-13 | 2009-06-17 | 페어차일드코리아반도체 주식회사 | Multi chip package |
US7781872B2 (en) * | 2007-12-19 | 2010-08-24 | Fairchild Semiconductor Corporation | Package with multiple dies |
US8106406B2 (en) * | 2008-01-09 | 2012-01-31 | Fairchild Semiconductor Corporation | Die package including substrate with molded device |
US7791084B2 (en) | 2008-01-09 | 2010-09-07 | Fairchild Semiconductor Corporation | Package with overlapping devices |
US7626249B2 (en) * | 2008-01-10 | 2009-12-01 | Fairchild Semiconductor Corporation | Flex clip connector for semiconductor device |
US20090194856A1 (en) * | 2008-02-06 | 2009-08-06 | Gomez Jocel P | Molded package assembly |
KR101524545B1 (en) * | 2008-02-28 | 2015-06-01 | 페어차일드코리아반도체 주식회사 | Power device package and the method of fabricating the same |
US8018054B2 (en) * | 2008-03-12 | 2011-09-13 | Fairchild Semiconductor Corporation | Semiconductor die package including multiple semiconductor dice |
US7768108B2 (en) | 2008-03-12 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die package including embedded flip chip |
KR101519062B1 (en) * | 2008-03-31 | 2015-05-11 | 페어차일드코리아반도체 주식회사 | Semiconductor Device Package |
US20090278241A1 (en) * | 2008-05-08 | 2009-11-12 | Yong Liu | Semiconductor die package including die stacked on premolded substrate including die |
DE102008042107A1 (en) * | 2008-09-15 | 2010-03-18 | Robert Bosch Gmbh | Electronic component and method for its production |
US8193618B2 (en) | 2008-12-12 | 2012-06-05 | Fairchild Semiconductor Corporation | Semiconductor die package with clip interconnection |
US7816784B2 (en) * | 2008-12-17 | 2010-10-19 | Fairchild Semiconductor Corporation | Power quad flat no-lead semiconductor die packages with isolated heat sink for high-voltage, high-power applications, systems using the same, and methods of making the same |
US7973393B2 (en) * | 2009-02-04 | 2011-07-05 | Fairchild Semiconductor Corporation | Stacked micro optocouplers and methods of making the same |
US8222718B2 (en) * | 2009-02-05 | 2012-07-17 | Fairchild Semiconductor Corporation | Semiconductor die package and method for making the same |
US20100289129A1 (en) * | 2009-05-14 | 2010-11-18 | Satya Chinnusamy | Copper plate bonding for high performance semiconductor packaging |
US8445375B2 (en) | 2009-09-29 | 2013-05-21 | Semiconductor Components Industries, Llc | Method for manufacturing a semiconductor component |
TWI445147B (en) * | 2009-10-14 | 2014-07-11 | Advanced Semiconductor Eng | Semiconductor device |
TW201113962A (en) * | 2009-10-14 | 2011-04-16 | Advanced Semiconductor Eng | Chip having metal pillar structure |
US20110186989A1 (en) * | 2010-02-04 | 2011-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device and Bump Formation Process |
US8296940B2 (en) | 2010-04-19 | 2012-10-30 | General Electric Company | Method of forming a micro pin hybrid interconnect array |
US8823166B2 (en) * | 2010-08-30 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar bumps and process for making same |
TWI478303B (en) | 2010-09-27 | 2015-03-21 | Advanced Semiconductor Eng | Chip having metal pillar and package having the same |
TWI451546B (en) | 2010-10-29 | 2014-09-01 | Advanced Semiconductor Eng | Stacked semiconductor package, semiconductor package thereof and method for making a semiconductor package |
TWI490117B (en) * | 2010-11-24 | 2015-07-01 | Nat Univ Tsing Hua | Heat spreading element with aln film and method for manufacturing the same |
US8421204B2 (en) | 2011-05-18 | 2013-04-16 | Fairchild Semiconductor Corporation | Embedded semiconductor power modules and packages |
DE102012102533B3 (en) | 2012-03-23 | 2013-08-22 | Infineon Technologies Austria Ag | Integrated power transistor circuit with current measuring cell and method for their preparation and an arrangement containing them |
US8884443B2 (en) | 2012-07-05 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
US8686568B2 (en) | 2012-09-27 | 2014-04-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package substrates having layered circuit segments, and related methods |
US9249014B2 (en) * | 2012-11-06 | 2016-02-02 | Infineon Technologies Austria Ag | Packaged nano-structured component and method of making a packaged nano-structured component |
US8937009B2 (en) * | 2013-04-25 | 2015-01-20 | International Business Machines Corporation | Far back end of the line metallization method and structures |
US10141201B2 (en) * | 2014-06-13 | 2018-11-27 | Taiwan Semiconductor Manufacturing Company | Integrated circuit packages and methods of forming same |
CN106463426B (en) * | 2014-06-27 | 2020-03-13 | 索尼公司 | Semiconductor device and method for manufacturing the same |
JP6458801B2 (en) * | 2014-06-27 | 2019-01-30 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
JP2017034059A (en) * | 2015-07-31 | 2017-02-09 | イビデン株式会社 | Printed wiring board, semiconductor package and manufacturing method for printed wiring board |
US9806052B2 (en) | 2015-09-15 | 2017-10-31 | Qualcomm Incorporated | Semiconductor package interconnect |
US10049893B2 (en) * | 2016-05-11 | 2018-08-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor device with a conductive post |
US10304697B2 (en) * | 2017-10-05 | 2019-05-28 | Amkor Technology, Inc. | Electronic device with top side pin array and manufacturing method thereof |
JP2020009823A (en) * | 2018-07-04 | 2020-01-16 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
Family Cites Families (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3429040A (en) | 1965-06-18 | 1969-02-25 | Ibm | Method of joining a component to a substrate |
US3401126A (en) | 1965-06-18 | 1968-09-10 | Ibm | Method of rendering noble metal conductive composition non-wettable by solder |
US4545610A (en) | 1983-11-25 | 1985-10-08 | International Business Machines Corporation | Method for forming elongated solder connections between a semiconductor device and a supporting substrate |
US5631447A (en) * | 1988-02-05 | 1997-05-20 | Raychem Limited | Uses of uniaxially electrically conductive articles |
US4980753A (en) * | 1988-11-21 | 1990-12-25 | Honeywell Inc. | Low-cost high-performance semiconductor chip package |
CA2017743C (en) * | 1989-06-30 | 1996-02-06 | William C. Hu | Ultra-tall indium or alloy bump array for ir detector hybrids and micro-electronics |
JP2555811B2 (en) | 1991-09-10 | 1996-11-20 | 富士通株式会社 | Flip chip bonding method for semiconductor chips |
US5288944A (en) | 1992-02-18 | 1994-02-22 | International Business Machines, Inc. | Pinned ceramic chip carrier |
US5359768A (en) | 1992-07-30 | 1994-11-01 | Intel Corporation | Method for mounting very small integrated circuit package on PCB |
US5346857A (en) | 1992-09-28 | 1994-09-13 | Motorola, Inc. | Method for forming a flip-chip bond from a gold-tin eutectic |
US5515604A (en) | 1992-10-07 | 1996-05-14 | Fujitsu Limited | Methods for making high-density/long-via laminated connectors |
US5334804A (en) | 1992-11-17 | 1994-08-02 | Fujitsu Limited | Wire interconnect structures for connecting an integrated circuit to a substrate |
US5329423A (en) * | 1993-04-13 | 1994-07-12 | Scholz Kenneth D | Compressive bump-and-socket interconnection scheme for integrated circuits |
US5355283A (en) | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
JP3258764B2 (en) * | 1993-06-01 | 2002-02-18 | 三菱電機株式会社 | Method for manufacturing resin-encapsulated semiconductor device, external lead-out electrode and method for manufacturing the same |
US6339191B1 (en) * | 1994-03-11 | 2002-01-15 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
US5542174A (en) | 1994-09-15 | 1996-08-06 | Intel Corporation | Method and apparatus for forming solder balls and solder columns |
KR0157284B1 (en) * | 1995-05-31 | 1999-02-18 | 김광호 | Printed circuit board of solder ball take-on groove furnished and this use of package ball grid array |
JPH0997791A (en) | 1995-09-27 | 1997-04-08 | Internatl Business Mach Corp <Ibm> | Bump structure, formation of bump and installation connection body |
US5567657A (en) * | 1995-12-04 | 1996-10-22 | General Electric Company | Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers |
US5639696A (en) | 1996-01-31 | 1997-06-17 | Lsi Logic Corporation | Microelectronic integrated circuit mounted on circuit board with solder column grid array interconnection, and method of fabricating the solder column grid array |
US5847929A (en) * | 1996-06-28 | 1998-12-08 | International Business Machines Corporation | Attaching heat sinks directly to flip chips and ceramic chip carriers |
US5817540A (en) * | 1996-09-20 | 1998-10-06 | Micron Technology, Inc. | Method of fabricating flip-chip on leads devices and resulting assemblies |
US6330967B1 (en) * | 1997-03-13 | 2001-12-18 | International Business Machines Corporation | Process to produce a high temperature interconnection |
US6013571A (en) * | 1997-06-16 | 2000-01-11 | Motorola, Inc. | Microelectronic assembly including columnar interconnections and method for forming same |
US6372553B1 (en) * | 1998-05-18 | 2002-04-16 | St Assembly Test Services, Pte Ltd | Disposable mold runner gate for substrate based electronic packages |
US5977640A (en) * | 1998-06-26 | 1999-11-02 | International Business Machines Corporation | Highly integrated chip-on-chip packaging |
US6133634A (en) | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
SG78324A1 (en) * | 1998-12-17 | 2001-02-20 | Eriston Technologies Pte Ltd | Bumpless flip chip assembly with strips-in-via and plating |
US6307755B1 (en) * | 1999-05-27 | 2001-10-23 | Richard K. Williams | Surface mount semiconductor package, die-leadframe combination and leadframe therefor and method of mounting leadframes to surfaces of semiconductor die |
US6201679B1 (en) * | 1999-06-04 | 2001-03-13 | California Micro Devices Corporation | Integrated electrical overload protection device and method of formation |
US6429533B1 (en) * | 1999-11-23 | 2002-08-06 | Bourns Inc. | Conductive polymer device and method of manufacturing same |
US6346469B1 (en) * | 2000-01-03 | 2002-02-12 | Motorola, Inc. | Semiconductor device and a process for forming the semiconductor device |
US6569753B1 (en) * | 2000-06-08 | 2003-05-27 | Micron Technology, Inc. | Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same |
US6391687B1 (en) * | 2000-10-31 | 2002-05-21 | Fairchild Semiconductor Corporation | Column ball grid array package |
US6597551B2 (en) * | 2000-12-13 | 2003-07-22 | Huladyne Corporation | Polymer current limiting device and method of manufacture |
US6541710B1 (en) * | 2001-11-16 | 2003-04-01 | Hewlett-Packard Company | Method and apparatus of supporting circuit component having a solder column array using interspersed rigid columns |
-
2001
- 2001-06-15 US US09/881,787 patent/US6683375B2/en not_active Expired - Lifetime
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2002
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- 2002-06-14 TW TW091113020A patent/TWI263317B/en not_active IP Right Cessation
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2003
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WO2002103755A3 (en) | 2003-04-03 |
US6683375B2 (en) | 2004-01-27 |
TWI263317B (en) | 2006-10-01 |
US20020192935A1 (en) | 2002-12-19 |
US7022548B2 (en) | 2006-04-04 |
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