WO2002097866A3 - Method of etching dielectric materials - Google Patents

Method of etching dielectric materials Download PDF

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Publication number
WO2002097866A3
WO2002097866A3 PCT/CA2002/000785 CA0200785W WO02097866A3 WO 2002097866 A3 WO2002097866 A3 WO 2002097866A3 CA 0200785 W CA0200785 W CA 0200785W WO 02097866 A3 WO02097866 A3 WO 02097866A3
Authority
WO
WIPO (PCT)
Prior art keywords
silicon oxide
plasma
subjecting
substrate
etch
Prior art date
Application number
PCT/CA2002/000785
Other languages
French (fr)
Other versions
WO2002097866A2 (en
Inventor
Boris Lamontagne
William Render
Andre Delage
Siegfried Janz
Lynden Erickson
Dan-Xia Xu
Pavel Cheben
Sylvain Charbonneau
Original Assignee
Lnl Technologies Canada Inc
Boris Lamontagne
William Render
Andre Delage
Siegfried Janz
Lynden Erickson
Dan-Xia Xu
Pavel Cheben
Sylvain Charbonneau
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lnl Technologies Canada Inc, Boris Lamontagne, William Render, Andre Delage, Siegfried Janz, Lynden Erickson, Dan-Xia Xu, Pavel Cheben, Sylvain Charbonneau filed Critical Lnl Technologies Canada Inc
Priority to AU2002302264A priority Critical patent/AU2002302264A1/en
Publication of WO2002097866A2 publication Critical patent/WO2002097866A2/en
Publication of WO2002097866A3 publication Critical patent/WO2002097866A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention relates to a method for dry etching of a silicon oxide substrate. The method comprises the steps of generating a non-etch plasma from an inert gas, subjecting the silicon oxide substrate to the resulting plasma to bring the silicon oxide to a stable elevated temperature, generating an etch plasma from a reactive gas or gas mixture containing a reactive gas, and subjecting the silicon oxide substrate, which is at the stable elevated temperature, to the resulting etch plasma to effect etching of the substrate. By subjecting the silicon oxide sample to an inert gas plasma prior to the etch step, and thus stabilizing the temperature of the silicon oxide, it has been found that a dramatic improvement in the verticality of etched side walls can be obtained.
PCT/CA2002/000785 2001-05-28 2002-05-28 Method of etching dielectric materials WO2002097866A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002302264A AU2002302264A1 (en) 2001-05-28 2002-05-28 Method of etching dielectric materials

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA2,349,033 2001-05-28
CA 2349033 CA2349033A1 (en) 2001-05-28 2001-05-28 Initial plasma treatment for vertical dry etching of sio2

Publications (2)

Publication Number Publication Date
WO2002097866A2 WO2002097866A2 (en) 2002-12-05
WO2002097866A3 true WO2002097866A3 (en) 2003-07-10

Family

ID=4169127

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2002/000785 WO2002097866A2 (en) 2001-05-28 2002-05-28 Method of etching dielectric materials

Country Status (3)

Country Link
AU (1) AU2002302264A1 (en)
CA (1) CA2349033A1 (en)
WO (1) WO2002097866A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8679970B2 (en) 2008-05-21 2014-03-25 International Business Machines Corporation Structure and process for conductive contact integration

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4445966A (en) * 1983-06-20 1984-05-01 Honeywell Inc. Method of plasma etching of films containing chromium
WO1996041369A1 (en) * 1995-06-07 1996-12-19 Lam Research Corporation Method and apparatus for controlling a temperature of a wafer
EP0805483A1 (en) * 1995-10-17 1997-11-05 Asm Japan K.K. Semiconductor treatment apparatus
US5877032A (en) * 1995-10-12 1999-03-02 Lucent Technologies Inc. Process for device fabrication in which the plasma etch is controlled by monitoring optical emission
JPH11162958A (en) * 1997-09-16 1999-06-18 Tokyo Electron Ltd Plasma treating device and plasma treating method
EP0926716A1 (en) * 1997-12-17 1999-06-30 Sumitomo Metal Industries, Ltd. Method and apparatus for plasma processing

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4445966A (en) * 1983-06-20 1984-05-01 Honeywell Inc. Method of plasma etching of films containing chromium
WO1996041369A1 (en) * 1995-06-07 1996-12-19 Lam Research Corporation Method and apparatus for controlling a temperature of a wafer
US5877032A (en) * 1995-10-12 1999-03-02 Lucent Technologies Inc. Process for device fabrication in which the plasma etch is controlled by monitoring optical emission
EP0805483A1 (en) * 1995-10-17 1997-11-05 Asm Japan K.K. Semiconductor treatment apparatus
JPH11162958A (en) * 1997-09-16 1999-06-18 Tokyo Electron Ltd Plasma treating device and plasma treating method
US20010008798A1 (en) * 1997-09-16 2001-07-19 Yoko Naito Plasma treatment system and method
EP0926716A1 (en) * 1997-12-17 1999-06-30 Sumitomo Metal Industries, Ltd. Method and apparatus for plasma processing

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ANONYMOUS: "Two Stage Process for Plasma Etching Cermet Films. January 1983.", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 25, no. 8, 1 January 1983 (1983-01-01), New York, US, pages 4352, XP002232697 *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 11 30 September 1999 (1999-09-30) *

Also Published As

Publication number Publication date
AU2002302264A1 (en) 2002-12-09
CA2349033A1 (en) 2002-11-28
WO2002097866A2 (en) 2002-12-05

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