WO2002093647A3 - Electronic package with high density interconnect and associated methods - Google Patents

Electronic package with high density interconnect and associated methods Download PDF

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Publication number
WO2002093647A3
WO2002093647A3 PCT/US2002/014879 US0214879W WO02093647A3 WO 2002093647 A3 WO2002093647 A3 WO 2002093647A3 US 0214879 W US0214879 W US 0214879W WO 02093647 A3 WO02093647 A3 WO 02093647A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
high density
package
bonding pads
pads
Prior art date
Application number
PCT/US2002/014879
Other languages
French (fr)
Other versions
WO2002093647A2 (en
Inventor
Robert Sankman
Tee Chong
Seng Hooi Ong
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to CN028098722A priority Critical patent/CN1526166B/en
Priority to KR1020037014825A priority patent/KR100692341B1/en
Priority to AU2002344331A priority patent/AU2002344331A1/en
Priority to JP2002590419A priority patent/JP2005515612A/en
Publication of WO2002093647A2 publication Critical patent/WO2002093647A2/en
Publication of WO2002093647A3 publication Critical patent/WO2002093647A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Abstract

An electronics package comprises an integrated circuit (IC) coupled to an IC substrate in a flip-chip ball grid array (FCBGA) configuration. The IC comprises a high density pattern of interconnect pads around its periphery for coupling to a corresponding pattern of bonding pads on the IC substrate. The substrate bonding pads are uniquely arranged to accommodate a high density of interconnect pads on the IC while taking into account various geometrical constraints on the substrate, such as bonding pad size, trace width, and trace spacing. In one embodiment, the substrate bonding pads are arranged in a zigzag pattern. In a further embodiment, the technique is used for bonding pads on a printed circuit board to which an IC package is coupled. Methods of fabrication, as well as application of the package to an electronic package, an electronic system, and a data processing system, are also described.
PCT/US2002/014879 2001-05-15 2002-05-10 Electronic package with high density interconnect and associated methods WO2002093647A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN028098722A CN1526166B (en) 2001-05-15 2002-05-10 Electronic package with high density interconnect and associated methods
KR1020037014825A KR100692341B1 (en) 2001-05-15 2002-05-10 Electronic package with high density interconnect and associated methods
AU2002344331A AU2002344331A1 (en) 2001-05-15 2002-05-10 Electronic package with high density interconnect and associated methods
JP2002590419A JP2005515612A (en) 2001-05-15 2002-05-10 Electronic package having high density wiring structure and related method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/858,238 2001-05-15
US09/858,238 US6664483B2 (en) 2001-05-15 2001-05-15 Electronic package with high density interconnect and associated methods

Publications (2)

Publication Number Publication Date
WO2002093647A2 WO2002093647A2 (en) 2002-11-21
WO2002093647A3 true WO2002093647A3 (en) 2003-11-20

Family

ID=25327828

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/014879 WO2002093647A2 (en) 2001-05-15 2002-05-10 Electronic package with high density interconnect and associated methods

Country Status (8)

Country Link
US (1) US6664483B2 (en)
JP (1) JP2005515612A (en)
KR (1) KR100692341B1 (en)
CN (1) CN1526166B (en)
AU (1) AU2002344331A1 (en)
MY (1) MY126218A (en)
TW (1) TW579583B (en)
WO (1) WO2002093647A2 (en)

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US8350384B2 (en) * 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
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US7659633B2 (en) 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
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US8347251B2 (en) * 2007-12-31 2013-01-01 Sandisk Corporation Integrated circuit and manufacturing process facilitating selective configuration for electromagnetic compatibility
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US9113547B2 (en) * 2008-10-24 2015-08-18 Intel Corporation Same layer microelectronic circuit patterning using hybrid laser projection patterning (LPP) and semi-additive patterning(SAP)
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Also Published As

Publication number Publication date
US20020172026A1 (en) 2002-11-21
CN1526166B (en) 2010-05-26
US6664483B2 (en) 2003-12-16
AU2002344331A1 (en) 2002-11-25
CN1526166A (en) 2004-09-01
JP2005515612A (en) 2005-05-26
WO2002093647A2 (en) 2002-11-21
KR100692341B1 (en) 2007-03-09
MY126218A (en) 2006-09-29
TW579583B (en) 2004-03-11
KR20040032098A (en) 2004-04-14

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