WO2002091451A3 - Methods of forming gap fill and layers formed thereby - Google Patents

Methods of forming gap fill and layers formed thereby Download PDF

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Publication number
WO2002091451A3
WO2002091451A3 PCT/US2002/014653 US0214653W WO02091451A3 WO 2002091451 A3 WO2002091451 A3 WO 2002091451A3 US 0214653 W US0214653 W US 0214653W WO 02091451 A3 WO02091451 A3 WO 02091451A3
Authority
WO
WIPO (PCT)
Prior art keywords
methods
layers formed
gap fill
forming gap
forming
Prior art date
Application number
PCT/US2002/014653
Other languages
French (fr)
Other versions
WO2002091451A2 (en
Inventor
Zheng Yuan
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of WO2002091451A2 publication Critical patent/WO2002091451A2/en
Publication of WO2002091451A3 publication Critical patent/WO2002091451A3/en

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Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04Coating on selected surface areas, e.g. using masks
    • C23C16/045Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • C23C16/401Oxides containing silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31608Deposition of SiO2
    • H01L21/31612Deposition of SiO2 on a silicon body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric

Abstract

A method of forming a fill layer over a layer in a semiconductor stack having gaps of high aspect ratio topography, and products produced thereby.
PCT/US2002/014653 2001-05-07 2002-05-07 Methods of forming gap fill and layers formed thereby WO2002091451A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/851,201 2001-05-07
US09/851,201 US6624091B2 (en) 2001-05-07 2001-05-07 Methods of forming gap fill and layers formed thereby

Publications (2)

Publication Number Publication Date
WO2002091451A2 WO2002091451A2 (en) 2002-11-14
WO2002091451A3 true WO2002091451A3 (en) 2003-07-03

Family

ID=25310207

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/014653 WO2002091451A2 (en) 2001-05-07 2002-05-07 Methods of forming gap fill and layers formed thereby

Country Status (2)

Country Link
US (1) US6624091B2 (en)
WO (1) WO2002091451A2 (en)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7141483B2 (en) 2002-09-19 2006-11-28 Applied Materials, Inc. Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill
US20070212850A1 (en) * 2002-09-19 2007-09-13 Applied Materials, Inc. Gap-fill depositions in the formation of silicon containing dielectric materials
US7431967B2 (en) 2002-09-19 2008-10-07 Applied Materials, Inc. Limited thermal budget formation of PMD layers
US7335609B2 (en) * 2004-08-27 2008-02-26 Applied Materials, Inc. Gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials
US7456116B2 (en) * 2002-09-19 2008-11-25 Applied Materials, Inc. Gap-fill depositions in the formation of silicon containing dielectric materials
WO2004027849A1 (en) * 2002-09-20 2004-04-01 Hitachi Kokusai Electric Inc. Method for manufacturing semiconductor device and substrate processing apparatus
US7205248B2 (en) * 2003-02-04 2007-04-17 Micron Technology, Inc. Method of eliminating residual carbon from flowable oxide fill
US20050100682A1 (en) * 2003-11-06 2005-05-12 Tokyo Electron Limited Method for depositing materials on a substrate
US7611758B2 (en) * 2003-11-06 2009-11-03 Tokyo Electron Limited Method of improving post-develop photoresist profile on a deposited dielectric film
US7297608B1 (en) 2004-06-22 2007-11-20 Novellus Systems, Inc. Method for controlling properties of conformal silica nanolaminates formed by rapid vapor deposition
US7202185B1 (en) * 2004-06-22 2007-04-10 Novellus Systems, Inc. Silica thin films produced by rapid surface catalyzed vapor deposition (RVD) using a nucleation layer
US7790633B1 (en) 2004-10-26 2010-09-07 Novellus Systems, Inc. Sequential deposition/anneal film densification method
US7294583B1 (en) 2004-12-23 2007-11-13 Novellus Systems, Inc. Methods for the use of alkoxysilanol precursors for vapor deposition of SiO2 films
US7482247B1 (en) 2004-12-30 2009-01-27 Novellus Systems, Inc. Conformal nanolaminate dielectric deposition and etch bag gap fill process
US20060188659A1 (en) * 2005-02-23 2006-08-24 Enthone Inc. Cobalt self-initiated electroless via fill for stacked memory cells
US7135418B1 (en) 2005-03-09 2006-11-14 Novellus Systems, Inc. Optimal operation of conformal silica deposition reactors
US7351285B2 (en) * 2005-03-29 2008-04-01 Tokyo Electron Limited Method and system for forming a variable thickness seed layer
US7972441B2 (en) 2005-04-05 2011-07-05 Applied Materials, Inc. Thermal oxidation of silicon using ozone
US7589028B1 (en) 2005-11-15 2009-09-15 Novellus Systems, Inc. Hydroxyl bond removal and film densification method for oxide films using microwave post treatment
US7491653B1 (en) 2005-12-23 2009-02-17 Novellus Systems, Inc. Metal-free catalysts for pulsed deposition layer process for conformal silica laminates
US7288463B1 (en) 2006-04-28 2007-10-30 Novellus Systems, Inc. Pulsed deposition layer gap fill with expansion material
US7625820B1 (en) 2006-06-21 2009-12-01 Novellus Systems, Inc. Method of selective coverage of high aspect ratio structures with a conformal film
EP1970468B1 (en) * 2007-03-05 2009-07-15 Applied Materials, Inc. Coating assembly and gas piping system
US9018108B2 (en) 2013-01-25 2015-04-28 Applied Materials, Inc. Low shrinkage dielectric films

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4949671A (en) * 1985-10-24 1990-08-21 Texas Instruments Incorporated Processing apparatus and method
US5763018A (en) * 1995-06-20 1998-06-09 Sony Corporation Method for forming dielectric layer
US6030460A (en) * 1996-05-24 2000-02-29 Lsi Logic Corporation Method and apparatus for forming dielectric films
EP1063692A1 (en) * 1999-06-22 2000-12-27 Applied Materials, Inc. Process for depositing a low dielectric constant film
US6194304B1 (en) * 1997-07-03 2001-02-27 Seiko Epson Corporation Semiconductor device and method of fabricating the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU4506993A (en) * 1992-07-04 1994-01-31 Christopher David Dobson A method of treating a semiconductor wafer
US6054379A (en) 1998-02-11 2000-04-25 Applied Materials, Inc. Method of depositing a low k dielectric with organo silane
US6068884A (en) 1998-04-28 2000-05-30 Silcon Valley Group Thermal Systems, Llc Method of making low κ dielectric inorganic/organic hybrid films

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4949671A (en) * 1985-10-24 1990-08-21 Texas Instruments Incorporated Processing apparatus and method
US5763018A (en) * 1995-06-20 1998-06-09 Sony Corporation Method for forming dielectric layer
US6030460A (en) * 1996-05-24 2000-02-29 Lsi Logic Corporation Method and apparatus for forming dielectric films
US6194304B1 (en) * 1997-07-03 2001-02-27 Seiko Epson Corporation Semiconductor device and method of fabricating the same
EP1063692A1 (en) * 1999-06-22 2000-12-27 Applied Materials, Inc. Process for depositing a low dielectric constant film

Also Published As

Publication number Publication date
WO2002091451A2 (en) 2002-11-14
US20020163028A1 (en) 2002-11-07
US6624091B2 (en) 2003-09-23

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