WO2002091450A3 - Ordered two-phase dielectric film, and semiconductor device containing the same - Google Patents

Ordered two-phase dielectric film, and semiconductor device containing the same Download PDF

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Publication number
WO2002091450A3
WO2002091450A3 PCT/US2002/013749 US0213749W WO02091450A3 WO 2002091450 A3 WO2002091450 A3 WO 2002091450A3 US 0213749 W US0213749 W US 0213749W WO 02091450 A3 WO02091450 A3 WO 02091450A3
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WO
WIPO (PCT)
Prior art keywords
phase
film
dielectric film
ordered
dielectric
Prior art date
Application number
PCT/US2002/013749
Other languages
French (fr)
Other versions
WO2002091450A2 (en
Inventor
Stephen Mcconnell Gates
Christopher B Murray
Satyanarayana V Nitta
Sampath Purushothaman
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Priority to IL15860902A priority Critical patent/IL158609A0/en
Priority to AT02731605T priority patent/ATE436088T1/en
Priority to KR1020037012932A priority patent/KR100655825B1/en
Priority to DE60232871T priority patent/DE60232871D1/en
Priority to JP2002588610A priority patent/JP3842220B2/en
Priority to AU2002303576A priority patent/AU2002303576A1/en
Priority to EP02731605A priority patent/EP1384256B1/en
Publication of WO2002091450A2 publication Critical patent/WO2002091450A2/en
Publication of WO2002091450A3 publication Critical patent/WO2002091450A3/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31695Deposition of porous oxides or porous glassy oxides or oxide based porous glass
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • HELECTRICITY
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract

A porous, low-k dielectric film that has good mechanical properties as well as a method of fabricating the film and the use of the film as a dielectric layer between metal wiring features are provided. The porous, low-k dielectric film includes a first phase of monodispersed pores having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially located on sites of a three-dimensional periodic lattice; and a second phase which is solid surrounding the first phase. Specifically, the second phase of the film includes (i) an ordered element that is composed of nanoparticles having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially arranged on sites of a three-dimensional periodic lattice, and (ii) a disordered element comprised of a dielectric material having a dielectric constant of about 2.8 or less.
PCT/US2002/013749 2001-05-03 2002-04-30 Ordered two-phase dielectric film, and semiconductor device containing the same WO2002091450A2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IL15860902A IL158609A0 (en) 2001-05-03 2002-04-30 Ordered two-phase dielectric film and semiconductor device containing the same
AT02731605T ATE436088T1 (en) 2001-05-03 2002-04-30 TWO-PHASE DIELECTRIC LAYER AND A SEMICONDUCTOR ARRANGEMENT CONTAINING THE SAME
KR1020037012932A KR100655825B1 (en) 2001-05-03 2002-04-30 Ordered two-phase dielectric film, and semiconductor device containing the same
DE60232871T DE60232871D1 (en) 2001-05-03 2002-04-30 TWO-PHASE ARRANGED DIELECTRIC LAYER, AND A SEMICONDUCTOR ARRANGEMENT CONTAINING THIS
JP2002588610A JP3842220B2 (en) 2001-05-03 2002-04-30 Porous low dielectric constant insulating film, interconnect structure, and method for producing porous low dielectric constant insulating film
AU2002303576A AU2002303576A1 (en) 2001-05-03 2002-04-30 Ordered two-phase dielectric film, and semiconductor device containing the same
EP02731605A EP1384256B1 (en) 2001-05-03 2002-04-30 Ordered two-phase dielectric film, and semiconductor device containing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/848,153 US6780499B2 (en) 2001-05-03 2001-05-03 Ordered two-phase dielectric film, and semiconductor device containing the same
US09/848,153 2001-05-03

Publications (2)

Publication Number Publication Date
WO2002091450A2 WO2002091450A2 (en) 2002-11-14
WO2002091450A3 true WO2002091450A3 (en) 2003-11-27

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PCT/US2002/013749 WO2002091450A2 (en) 2001-05-03 2002-04-30 Ordered two-phase dielectric film, and semiconductor device containing the same

Country Status (12)

Country Link
US (1) US6780499B2 (en)
EP (1) EP1384256B1 (en)
JP (1) JP3842220B2 (en)
KR (1) KR100655825B1 (en)
CN (1) CN100356521C (en)
AT (1) ATE436088T1 (en)
AU (1) AU2002303576A1 (en)
DE (1) DE60232871D1 (en)
IL (1) IL158609A0 (en)
MY (1) MY126213A (en)
TW (1) TW538538B (en)
WO (1) WO2002091450A2 (en)

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US6593247B1 (en) * 1998-02-11 2003-07-15 Applied Materials, Inc. Method of depositing low k films using an oxidizing plasma
US6054379A (en) 1998-02-11 2000-04-25 Applied Materials, Inc. Method of depositing a low k dielectric with organo silane
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FR2827854B1 (en) * 2001-07-25 2003-09-19 Saint Gobain Rech SUBSTRATE COATED WITH A COMPOSITE FILM, MANUFACTURING METHOD AND APPLICATIONS
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JP2007515361A (en) * 2003-03-06 2007-06-14 レンセラー・ポリテクニック・インスティチュート Rapid generation of nanoparticles from bulk solids at room temperature
US7288292B2 (en) * 2003-03-18 2007-10-30 International Business Machines Corporation Ultra low k (ULK) SiCOH film and method
US7030468B2 (en) * 2004-01-16 2006-04-18 International Business Machines Corporation Low k and ultra low k SiCOH dielectric films and methods to form the same
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