WO2002084428A3 - High speed interface with looped bus - Google Patents

High speed interface with looped bus Download PDF

Info

Publication number
WO2002084428A3
WO2002084428A3 PCT/US2001/051615 US0151615W WO02084428A3 WO 2002084428 A3 WO2002084428 A3 WO 2002084428A3 US 0151615 W US0151615 W US 0151615W WO 02084428 A3 WO02084428 A3 WO 02084428A3
Authority
WO
WIPO (PCT)
Prior art keywords
bus
looping
data
interface circuit
high speed
Prior art date
Application number
PCT/US2001/051615
Other languages
French (fr)
Other versions
WO2002084428A2 (en
Inventor
Terry R Lee
Roy Greeff
David Ovard
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to AU2001297792A priority Critical patent/AU2001297792A1/en
Publication of WO2002084428A2 publication Critical patent/WO2002084428A2/en
Publication of WO2002084428A3 publication Critical patent/WO2002084428A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and associated apparatus is provided for improving the performance of a high speed memory bus by substantially eliminating bus reflections caused by electrical stubs. The stubs are substantially eliminated by connecting system components in a substantially stubless configuration using a looping bus for continuing the looping through each device. The invention also provides an interface circuit that enables data communications between devices of different technologies. The interface circuit connects to the looping data bus and includes a circuit for providing voltage level, encoding type, and data rate conversions for data received from the looping data bus and intended for use on a second data bus connected to the interface circuit.
PCT/US2001/051615 2000-12-22 2001-12-11 High speed interface with looped bus WO2002084428A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001297792A AU2001297792A1 (en) 2000-12-22 2001-12-11 High speed interface with looped bus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/741,821 US6934785B2 (en) 2000-12-22 2000-12-22 High speed interface with looped bus
US09/741,821 2000-12-22

Publications (2)

Publication Number Publication Date
WO2002084428A2 WO2002084428A2 (en) 2002-10-24
WO2002084428A3 true WO2002084428A3 (en) 2003-01-23

Family

ID=24982350

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/051615 WO2002084428A2 (en) 2000-12-22 2001-12-11 High speed interface with looped bus

Country Status (3)

Country Link
US (3) US6934785B2 (en)
AU (1) AU2001297792A1 (en)
WO (1) WO2002084428A2 (en)

Families Citing this family (136)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6597197B1 (en) * 1999-08-27 2003-07-22 Intel Corporation I2C repeater with voltage translation
US6745268B1 (en) * 2000-08-11 2004-06-01 Micron Technology, Lnc. Capacitive multidrop bus compensation
US8149048B1 (en) 2000-10-26 2012-04-03 Cypress Semiconductor Corporation Apparatus and method for programmable power management in a programmable analog circuit block
US6724220B1 (en) 2000-10-26 2004-04-20 Cyress Semiconductor Corporation Programmable microcontroller architecture (mixed analog/digital)
US8176296B2 (en) 2000-10-26 2012-05-08 Cypress Semiconductor Corporation Programmable microcontroller architecture
US7765095B1 (en) 2000-10-26 2010-07-27 Cypress Semiconductor Corporation Conditional branching in an in-circuit emulation system
US8103496B1 (en) 2000-10-26 2012-01-24 Cypress Semicondutor Corporation Breakpoint control in an in-circuit emulation system
US8160864B1 (en) 2000-10-26 2012-04-17 Cypress Semiconductor Corporation In-circuit emulator and pod synchronized boot
DE10107100A1 (en) * 2001-02-13 2002-12-05 Profichip Gmbh Plug device with integrated diagnosis and evaluation circuit and switchable terminating resistor
US7406674B1 (en) 2001-10-24 2008-07-29 Cypress Semiconductor Corporation Method and apparatus for generating microcontroller configuration information
US8078970B1 (en) 2001-11-09 2011-12-13 Cypress Semiconductor Corporation Graphical user interface with user-selectable list-box
US8042093B1 (en) 2001-11-15 2011-10-18 Cypress Semiconductor Corporation System providing automatic source code generation for personalization and parameterization of user modules
US7774190B1 (en) 2001-11-19 2010-08-10 Cypress Semiconductor Corporation Sleep and stall in an in-circuit emulation system
US6971004B1 (en) 2001-11-19 2005-11-29 Cypress Semiconductor Corp. System and method of dynamically reconfiguring a programmable integrated circuit
US7770113B1 (en) 2001-11-19 2010-08-03 Cypress Semiconductor Corporation System and method for dynamically generating a configuration datasheet
US7844437B1 (en) 2001-11-19 2010-11-30 Cypress Semiconductor Corporation System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit
US8069405B1 (en) 2001-11-19 2011-11-29 Cypress Semiconductor Corporation User interface for efficiently browsing an electronic document using data-driven tabs
JP2003167839A (en) * 2001-11-29 2003-06-13 Elpida Memory Inc Semiconductor memory device
DE10162583B4 (en) * 2001-12-19 2004-05-13 Infineon Technologies Ag Branched command / address bus architecture for registered storage devices
US8103497B1 (en) 2002-03-28 2012-01-24 Cypress Semiconductor Corporation External interface for event architecture
US7308608B1 (en) 2002-05-01 2007-12-11 Cypress Semiconductor Corporation Reconfigurable testing system and method
EP1383052B1 (en) * 2002-07-15 2006-03-29 Infineon Technologies AG Memory system
JP4094370B2 (en) * 2002-07-31 2008-06-04 エルピーダメモリ株式会社 Memory module and memory system
DE10237174B4 (en) * 2002-08-14 2012-06-21 Robert Bosch Gmbh Method and device for the serial transmission of data from a processor module to at least one peripheral element
US7761845B1 (en) 2002-09-09 2010-07-20 Cypress Semiconductor Corporation Method for parameterizing a user module
KR100464437B1 (en) * 2002-11-20 2004-12-31 삼성전자주식회사 On-Die Termination circuit and method for reducing on-chip DC current and memory system including memory device having the same
US7142461B2 (en) * 2002-11-20 2006-11-28 Micron Technology, Inc. Active termination control though on module register
JP4072424B2 (en) * 2002-12-02 2008-04-09 エルピーダメモリ株式会社 Memory system and control method thereof
US7096301B2 (en) * 2003-01-13 2006-08-22 Texas Instruments Incorporated Communications interface for enabling extension of an internal common bus architecture (CBA)
US7308524B2 (en) * 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
WO2004092904A2 (en) * 2003-04-10 2004-10-28 Silicon Pipe, Inc. Memory system having a multiplexed high-speed channel
US20040255070A1 (en) * 2003-06-12 2004-12-16 Larson Thane M. Inter-integrated circuit router for supporting independent transmission rates
US7194572B2 (en) * 2003-08-08 2007-03-20 Intel Corporation Memory system and method to reduce reflection and signal degradation
US7133962B2 (en) * 2003-09-09 2006-11-07 Intel Corporation Circulator chain memory command and address bus topology
US7779212B2 (en) 2003-10-17 2010-08-17 Micron Technology, Inc. Method and apparatus for sending data from multiple sources over a communications bus
CN100452032C (en) * 2003-10-27 2009-01-14 特博数据实验室公司 Distributed memory type information processing system
US7085863B2 (en) * 2003-10-30 2006-08-01 International Business Machines Corporation I2C device including bus switches and programmable address
US7143207B2 (en) 2003-11-14 2006-11-28 Intel Corporation Data accumulation between data path having redrive circuit and memory device
US7043591B2 (en) * 2003-11-19 2006-05-09 Lsi Logic Corporation Cross switch supporting simultaneous data traffic in opposing directions
TWI292533B (en) * 2003-11-20 2008-01-11 Sunplus Technology Co Ltd System for accessing a plurality of devices by using single bus and control apparatus therein
US7031221B2 (en) * 2003-12-30 2006-04-18 Intel Corporation Fixed phase clock and strobe signals in daisy chained chips
US7009894B2 (en) * 2004-02-19 2006-03-07 Intel Corporation Dynamically activated memory controller data termination
US7432774B2 (en) * 2004-02-27 2008-10-07 Micron Technology, Inc. Microstrip line dielectric overlay
US7295049B1 (en) 2004-03-25 2007-11-13 Cypress Semiconductor Corporation Method and circuit for rapid alignment of signals
US20050228912A1 (en) * 2004-03-30 2005-10-13 Walker Clinton F Memory address bus termination control
US7389375B2 (en) * 2004-07-30 2008-06-17 International Business Machines Corporation System, method and storage medium for a multi-mode memory buffer device
US7296129B2 (en) 2004-07-30 2007-11-13 International Business Machines Corporation System, method and storage medium for providing a serialized memory interface with a bus repeater
US7224595B2 (en) 2004-07-30 2007-05-29 International Business Machines Corporation 276-Pin buffered memory module with enhanced fault tolerance
US8069436B2 (en) 2004-08-13 2011-11-29 Cypress Semiconductor Corporation Providing hardware independence to automate code generation of processing device firmware
US8286125B2 (en) 2004-08-13 2012-10-09 Cypress Semiconductor Corporation Model for a hardware device-independent method of defining embedded firmware for programmable systems
US7512762B2 (en) * 2004-10-29 2009-03-31 International Business Machines Corporation System, method and storage medium for a memory subsystem with positional read data latency
US7299313B2 (en) * 2004-10-29 2007-11-20 International Business Machines Corporation System, method and storage medium for a memory subsystem command interface
US7331010B2 (en) 2004-10-29 2008-02-12 International Business Machines Corporation System, method and storage medium for providing fault detection and correction in a memory subsystem
US7501586B2 (en) * 2004-10-29 2009-03-10 Intel Corporation Apparatus and method for improving printed circuit board signal layer transitions
US7305574B2 (en) * 2004-10-29 2007-12-04 International Business Machines Corporation System, method and storage medium for bus calibration in a memory subsystem
US7332976B1 (en) 2005-02-04 2008-02-19 Cypress Semiconductor Corporation Poly-phase frequency synthesis oscillator
US7990983B2 (en) 2005-03-31 2011-08-02 Intel Corporation Modular interconnect structure
US7426632B2 (en) 2005-03-31 2008-09-16 Intel Corporation Clock distribution for interconnect structures
US9384818B2 (en) 2005-04-21 2016-07-05 Violin Memory Memory power management
US8112655B2 (en) * 2005-04-21 2012-02-07 Violin Memory, Inc. Mesosynchronous data bus apparatus and method of data transmission
US9582449B2 (en) 2005-04-21 2017-02-28 Violin Memory, Inc. Interconnection system
US8452929B2 (en) * 2005-04-21 2013-05-28 Violin Memory Inc. Method and system for storage of data in non-volatile media
US9286198B2 (en) 2005-04-21 2016-03-15 Violin Memory Method and system for storage of data in non-volatile media
KR101331569B1 (en) * 2005-04-21 2013-11-21 바이올린 메모리 인코포레이티드 Interconnection System
US7400183B1 (en) 2005-05-05 2008-07-15 Cypress Semiconductor Corporation Voltage controlled oscillator delay cell and method
US8089461B2 (en) 2005-06-23 2012-01-03 Cypress Semiconductor Corporation Touch wake for electronic devices
US20070057695A1 (en) * 2005-09-15 2007-03-15 Hermann Ruckerbauer Semiconductor memory chip with re-drive unit for electrical signals
US7555670B2 (en) * 2005-10-26 2009-06-30 Intel Corporation Clocking architecture using a bidirectional clock port
US7478259B2 (en) * 2005-10-31 2009-01-13 International Business Machines Corporation System, method and storage medium for deriving clocks in a memory system
US7685392B2 (en) 2005-11-28 2010-03-23 International Business Machines Corporation Providing indeterminate read data latency in a memory system
US8085067B1 (en) 2005-12-21 2011-12-27 Cypress Semiconductor Corporation Differential-to-single ended signal converter circuit and method
US7519754B2 (en) * 2005-12-28 2009-04-14 Silicon Storage Technology, Inc. Hard disk drive cache memory and playback device
US20070147115A1 (en) * 2005-12-28 2007-06-28 Fong-Long Lin Unified memory and controller
CN1996273A (en) * 2006-01-04 2007-07-11 鸿富锦精密工业（深圳）有限公司 High-speed signal transmission circuit
US9098641B1 (en) * 2006-01-30 2015-08-04 Cypress Semiconductor Corporation Configurable bus
KR101239338B1 (en) * 2006-03-09 2013-03-18 삼성전자주식회사 Display device and method of the driving
US8067948B2 (en) 2006-03-27 2011-11-29 Cypress Semiconductor Corporation Input/output multiplexer bus
US7640386B2 (en) * 2006-05-24 2009-12-29 International Business Machines Corporation Systems and methods for providing memory modules with multiple hub devices
US7610408B2 (en) * 2006-06-29 2009-10-27 Agilent Technologies, Inc. Automatic link commissioning
US7546410B2 (en) * 2006-07-26 2009-06-09 International Business Machines Corporation Self timed memory chip having an apportionable data bus
US7545664B2 (en) * 2006-07-26 2009-06-09 International Business Machines Corporation Memory system having self timed daisy chained memory chips
US7490186B2 (en) * 2006-07-26 2009-02-10 International Business Machines Corporation Memory system having an apportionable data bus and daisy chained memory chips
US7577811B2 (en) * 2006-07-26 2009-08-18 International Business Machines Corporation Memory controller for daisy chained self timed memory chips
US7660940B2 (en) * 2006-07-26 2010-02-09 International Business Machines Corporation Carrier having daisy chain of self timed memory chips
US7627711B2 (en) * 2006-07-26 2009-12-01 International Business Machines Corporation Memory controller for daisy chained memory chips
US7673093B2 (en) * 2006-07-26 2010-03-02 International Business Machines Corporation Computer system having daisy chained memory chips
US7620763B2 (en) * 2006-07-26 2009-11-17 International Business Machines Corporation Memory chip having an apportionable data bus
US7480201B2 (en) * 2006-07-26 2009-01-20 International Business Machines Corporation Daisy chainable memory chip
US7660942B2 (en) * 2006-07-26 2010-02-09 International Business Machines Corporation Daisy chainable self timed memory chip
US7844769B2 (en) * 2006-07-26 2010-11-30 International Business Machines Corporation Computer system having an apportionable data bus and daisy chained memory chips
US7617350B2 (en) * 2006-07-26 2009-11-10 International Business Machines Corporation Carrier having daisy chained memory chips
KR100782853B1 (en) * 2006-07-31 2007-12-06 삼성전자주식회사 Ieee 1394 audio/video network system and method for constituting network
US7493439B2 (en) * 2006-08-01 2009-02-17 International Business Machines Corporation Systems and methods for providing performance monitoring in a memory system
US7669086B2 (en) * 2006-08-02 2010-02-23 International Business Machines Corporation Systems and methods for providing collision detection in a memory system
US7587559B2 (en) * 2006-08-10 2009-09-08 International Business Machines Corporation Systems and methods for memory module power management
US7870459B2 (en) 2006-10-23 2011-01-11 International Business Machines Corporation High density high reliability memory module with power gating and a fault tolerant address and command bus
US8028186B2 (en) 2006-10-23 2011-09-27 Violin Memory, Inc. Skew management in an interconnection system
WO2008079911A1 (en) 2006-12-21 2008-07-03 Rambus Inc. Dynamic on-die termination of address and command signals
US7721140B2 (en) 2007-01-02 2010-05-18 International Business Machines Corporation Systems and methods for improving serviceability of a memory system
US7603526B2 (en) * 2007-01-29 2009-10-13 International Business Machines Corporation Systems and methods for providing dynamic memory pre-fetch
US7606988B2 (en) * 2007-01-29 2009-10-20 International Business Machines Corporation Systems and methods for providing a dynamic memory bank page policy
US8092083B2 (en) 2007-04-17 2012-01-10 Cypress Semiconductor Corporation Temperature sensor with digital bandgap
US8516025B2 (en) 2007-04-17 2013-08-20 Cypress Semiconductor Corporation Clock driven dynamic datapath chaining
US9564902B2 (en) 2007-04-17 2017-02-07 Cypress Semiconductor Corporation Dynamically configurable and re-configurable data path
US8130025B2 (en) 2007-04-17 2012-03-06 Cypress Semiconductor Corporation Numerical band gap
US7737724B2 (en) 2007-04-17 2010-06-15 Cypress Semiconductor Corporation Universal digital block interconnection and channel routing
US8026739B2 (en) 2007-04-17 2011-09-27 Cypress Semiconductor Corporation System level interconnect with programmable switching
US8040266B2 (en) 2007-04-17 2011-10-18 Cypress Semiconductor Corporation Programmable sigma-delta analog-to-digital converter
US9720805B1 (en) 2007-04-25 2017-08-01 Cypress Semiconductor Corporation System and method for controlling a target device
US8266575B1 (en) 2007-04-25 2012-09-11 Cypress Semiconductor Corporation Systems and methods for dynamically reconfiguring a programmable system on a chip
US8065653B1 (en) 2007-04-25 2011-11-22 Cypress Semiconductor Corporation Configuration of programmable IC design elements
KR100901394B1 (en) * 2007-05-15 2009-06-05 삼성전자주식회사 Data transmission device and data transmission method
US20090063786A1 (en) * 2007-08-29 2009-03-05 Hakjune Oh Daisy-chain memory configuration and usage
US8049569B1 (en) 2007-09-05 2011-11-01 Cypress Semiconductor Corporation Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes
US7870366B2 (en) * 2007-09-22 2011-01-11 Hirak Mitra Chained operation of functional components with DONE and GO registers storing memory address for writing and reading linking signal value
US20090119114A1 (en) * 2007-11-02 2009-05-07 David Alaniz Systems and Methods for Enabling Customer Service
US8825939B2 (en) * 2007-12-12 2014-09-02 Conversant Intellectual Property Management Inc. Semiconductor memory device suitable for interconnection in a ring topology
US8135890B2 (en) * 2008-05-28 2012-03-13 Rambus Inc. Selective switching of a memory bus
US9122809B2 (en) * 2008-07-01 2015-09-01 Hewlett-Packard Development Company, L.P. Segmenting bus topology
DE102008050102B4 (en) * 2008-10-06 2010-11-04 Phoenix Contact Gmbh & Co. Kg Communication entity for communication via a bus-oriented communication network
RU2413290C2 (en) * 2009-04-16 2011-02-27 Николай Иванович Пальченко Computer architecture with self-contained modules
US9448964B2 (en) 2009-05-04 2016-09-20 Cypress Semiconductor Corporation Autonomous control in a programmable system
JP2012527037A (en) * 2009-05-15 2012-11-01 トムソン ライセンシング System and method for sharing memory
US8164936B2 (en) * 2009-10-14 2012-04-24 Seagate Technology Llc Switched memory devices
US20110193854A1 (en) * 2010-02-11 2011-08-11 Apple Inc. Synchronous bus driving method
US8582382B2 (en) * 2010-03-23 2013-11-12 Mosaid Technologies Incorporated Memory system having a plurality of serially connected devices
US9003096B2 (en) * 2011-03-16 2015-04-07 Texas Instruments Incorporated Serial interface
CN102339266B (en) * 2011-10-28 2013-08-14 中国兵器工业集团第二一四研究所苏州研发中心 Single data line bidirectional dual voltage communication interface circuit
EP2844518B1 (en) * 2012-04-30 2018-11-28 Thermo King Corporation Transport refrigeration system controller to engine control unit interface
US9190133B2 (en) * 2013-03-11 2015-11-17 Micron Technology, Inc. Apparatuses and methods for a memory die architecture including an interface memory
US9946675B2 (en) * 2013-03-13 2018-04-17 Atieva, Inc. Fault-tolerant loop for a communication bus
GB201507495D0 (en) * 2015-04-30 2015-06-17 Cooper Technologies Co Bus network terminator
US10409754B2 (en) * 2016-04-28 2019-09-10 Smart Modular Technologies, Inc. Interconnected memory system and method of operation thereof
CN112332881B (en) * 2020-10-19 2022-04-26 深圳市信锐网科技术有限公司 Enabling circuit and communication device
KR20220112322A (en) 2021-02-03 2022-08-11 삼성전자주식회사 Interface circuit that controlling output impedance of transmitting circuit and image sensor including the same
CN116455691A (en) * 2022-01-06 2023-07-18 华为技术有限公司 Communication device and system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4974152A (en) * 1986-05-15 1990-11-27 Yves Guiffant Inserted device for independently connecting auxiliary storage units to a data-processing assembly
WO1999019874A1 (en) * 1997-10-10 1999-04-22 Rambus Incorporated Power control system for synchronous memory device
WO1999030240A1 (en) * 1997-12-05 1999-06-17 Intel Corporation Memory system including a memory module having a memory module controller

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4470114A (en) * 1982-03-01 1984-09-04 Burroughs Corporation High speed interconnection network for a cluster of processors
JP3118266B2 (en) * 1990-03-06 2000-12-18 ゼロックス コーポレイション Synchronous segment bus and bus communication method
US5081648A (en) * 1990-03-12 1992-01-14 The Boeing Company Current mode data bus digital communications system
US5452330A (en) * 1992-07-06 1995-09-19 Digital Equipment Corporation Bus-oriented switching system for asynchronous transfer mode
US5631906A (en) * 1993-03-11 1997-05-20 Liu; Zheng Medium access control protocol for single bus fair access local area network
US5955889A (en) * 1994-05-20 1999-09-21 Fujitsu Limited Electronic circuit apparatus for transmitting signals through a bus and semiconductor device for generating a predetermined stable voltage
US5623644A (en) * 1994-08-25 1997-04-22 Intel Corporation Point-to-point phase-tolerant communication
US6014037A (en) * 1997-03-27 2000-01-11 Lucent Technologies Inc. Method and component arrangement for enhancing signal integrity
US6233253B1 (en) * 1997-05-23 2001-05-15 Thomson Licensing S.A. System for digital data format conversion and bit stream generation
US6182178B1 (en) * 1998-06-30 2001-01-30 International Business Machines Corporation Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across a PCI host bridge supporting multiple PCI buses
US6356984B1 (en) * 1998-06-30 2002-03-12 Sun Microsystems, Inc. Digital data processing system having a data bus and a control bus
US6338107B1 (en) * 1998-12-16 2002-01-08 International Business Machines Corporation Method and system for providing hot plug of adapter cards in an expanded slot environment
AUPQ005099A0 (en) * 1999-04-29 1999-05-20 Canon Kabushiki Kaisha Sequential bus architecture
US6286067B1 (en) * 1999-09-21 2001-09-04 Sony Corporation Method and system for the simplification of leaf-limited bridges
US6662260B1 (en) * 2000-03-28 2003-12-09 Analog Devices, Inc. Electronic circuits with dynamic bus partitioning
US6745268B1 (en) * 2000-08-11 2004-06-01 Micron Technology, Lnc. Capacitive multidrop bus compensation
US6658509B1 (en) * 2000-10-03 2003-12-02 Intel Corporation Multi-tier point-to-point ring memory interface
US7010637B2 (en) * 2002-05-02 2006-03-07 Intel Corporation Single-ended memory interface system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4974152A (en) * 1986-05-15 1990-11-27 Yves Guiffant Inserted device for independently connecting auxiliary storage units to a data-processing assembly
WO1999019874A1 (en) * 1997-10-10 1999-04-22 Rambus Incorporated Power control system for synchronous memory device
WO1999030240A1 (en) * 1997-12-05 1999-06-17 Intel Corporation Memory system including a memory module having a memory module controller

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KONISHI Y ET AL: "INTERFACE TECHNOLOGIES FOR MEMORIES AND ASICS - REVIEW AND FUTURE DIRECTION", IEICE TRANSACTIONS ON ELECTRONICS, INSTITUTE OF ELECTRONICS INFORMATION AND COMM. ENG. TOKYO, JP, vol. E82-C, no. 3, March 1999 (1999-03-01), pages 438 - 447, XP000896558, ISSN: 0916-8524 *
MONCAYO A ET AL: "Physical layer design of a 1.6 GB/s DRAM bus", ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 1999 SAN DIEGO, CA, USA 25-27 OCT. 1999, PISCATAWAY, NJ, USA,IEEE, US, 25 October 1999 (1999-10-25), pages 11 - 14, XP010367361, ISBN: 0-7803-5597-0 *

Also Published As

Publication number Publication date
US6934785B2 (en) 2005-08-23
AU2001297792A1 (en) 2002-10-28
US20050235090A1 (en) 2005-10-20
US20020083255A1 (en) 2002-06-27
WO2002084428A2 (en) 2002-10-24
US6871253B2 (en) 2005-03-22
US20040225770A1 (en) 2004-11-11

Similar Documents

Publication Publication Date Title
WO2002084428A3 (en) High speed interface with looped bus
WO2002019623A3 (en) A home network system and method
WO2001067787A3 (en) Method and apparatus for participating in group communication services in an existing communication system
WO1999023787A3 (en) Bidirectional communication port for digital signal processor
WO1995027353A3 (en) Simultaneous transmission of high and low speed signals
WO2002048750A3 (en) Interfacing fiber optic data with electrical power systems
MY118030A (en) Terminal apparatus
EP1487150A3 (en) Method and apparatus for determination of network topology
KR20150030712A (en) Simultaneous transmission of clock and bidirectional data over a communication channel
WO2004095703A3 (en) Method and apparatus for communication with a programmable logic device using serial transceivers
WO2002095945A3 (en) Method and apparatus for impedance matching in a transmission
WO2002046891A3 (en) Enabling of devices
GB2387943A (en) Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion
KR20110030484A (en) A high speed data transmission method and corresponding devices
KR880700576A (en) Digital transmission line loop forming apparatus and method of channel device
WO1999007082A3 (en) Cable interface for data and power supply
CN108347660B (en) Analog relay access device
AU5442099A (en) Terminator unit for wiring networks
AU2001251170A1 (en) Method and apparatus for monitoring access to a communications circuit
WO2002009376A1 (en) Data transmission device, data transfer system and method
WO2005006625A3 (en) Device identification
US20080205450A1 (en) High speed power line network connector and method for power line networking
JPH06224976A (en) Interface conversion circuit for half duplex serial transmission
EP0886402A3 (en) Method and apparatus for electronic communication
CN204231360U (en) A kind of Optical Fiber Transmission access device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP