WO2002082540A1 - Dispositif a semi-conducteurs, son procede de fabrication et substrat semi-conducteur connexe - Google Patents

Dispositif a semi-conducteurs, son procede de fabrication et substrat semi-conducteur connexe Download PDF

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Publication number
WO2002082540A1
WO2002082540A1 PCT/JP2001/002755 JP0102755W WO02082540A1 WO 2002082540 A1 WO2002082540 A1 WO 2002082540A1 JP 0102755 W JP0102755 W JP 0102755W WO 02082540 A1 WO02082540 A1 WO 02082540A1
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WO
WIPO (PCT)
Prior art keywords
chip
semiconductor
functional
manufacture
functional chip
Prior art date
Application number
PCT/JP2001/002755
Other languages
English (en)
French (fr)
Inventor
Yoshiharu Kato
Satoru Kawamoto
Fumihiko Taniguchi
Tetsuya Hiraoka
Akira Takashima
Original Assignee
Fujitsu Limited
Fujitsu Vlsi Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited, Fujitsu Vlsi Limited filed Critical Fujitsu Limited
Priority to PCT/JP2001/002755 priority Critical patent/WO2002082540A1/ja
Priority to JP2002536861A priority patent/JP4091838B2/ja
Priority to TW090108763A priority patent/TW488001B/zh
Priority to US10/058,877 priority patent/US6972487B2/en
Publication of WO2002082540A1 publication Critical patent/WO2002082540A1/ja
Priority to US11/080,414 priority patent/US20050161794A1/en
Priority to US11/448,863 priority patent/US20060226529A1/en

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    • H01L22/22Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
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PCT/JP2001/002755 2001-03-30 2001-03-30 Dispositif a semi-conducteurs, son procede de fabrication et substrat semi-conducteur connexe WO2002082540A1 (fr)

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PCT/JP2001/002755 WO2002082540A1 (fr) 2001-03-30 2001-03-30 Dispositif a semi-conducteurs, son procede de fabrication et substrat semi-conducteur connexe
JP2002536861A JP4091838B2 (ja) 2001-03-30 2001-03-30 半導体装置
TW090108763A TW488001B (en) 2001-03-30 2001-04-12 Semiconductor device, manufacturing method thereof, and semiconductor substrate
US10/058,877 US6972487B2 (en) 2001-03-30 2002-01-25 Multi chip package structure having a plurality of semiconductor chips mounted in the same package
US11/080,414 US20050161794A1 (en) 2001-03-30 2005-03-16 Semiconductor device, method for manufacturing the semiconductor device and semiconductor substrate
US11/448,863 US20060226529A1 (en) 2001-03-30 2006-06-08 Semiconductor device, method for manufacturing the semiconductor device and semiconductor substrate

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006013495A (ja) * 2004-06-22 2006-01-12 Samsung Electronics Co Ltd 他のチップを経由して入力信号を伝達する集積回路装置及び集積回路マルチチップパッケージ
JP2006295059A (ja) * 2005-04-14 2006-10-26 Denso Corp 半導体装置およびその製造方法
JP2007071733A (ja) * 2005-09-07 2007-03-22 Fuji Electric Holdings Co Ltd 光学式絶対値エンコーダ
JP2007158244A (ja) * 2005-12-08 2007-06-21 Fujitsu Ltd 半導体装置に配設される中継部材、半導体装置、及び半導体装置の製造方法
JP2008027934A (ja) * 2006-07-18 2008-02-07 Fujitsu Ltd 半導体装置及びその製造方法
JP2008545255A (ja) * 2005-06-28 2008-12-11 インテル・コーポレーション パッケージング・ロジックおよびメモリ集積回路
US7466158B2 (en) 2004-10-21 2008-12-16 Elpida Memory, Inc. Multilayer semiconductor device
US7977159B2 (en) 2001-07-10 2011-07-12 Kabushiki Kaisha Toshiba Memory chip and semiconductor device using the memory chip and manufacturing method of those
JP2011249838A (ja) * 2011-08-04 2011-12-08 Renesas Electronics Corp 半導体装置及びその製造方法
JP2012256741A (ja) * 2011-06-09 2012-12-27 Shinko Electric Ind Co Ltd 半導体パッケージ
JP2015507372A (ja) * 2012-02-08 2015-03-05 ザイリンクス インコーポレイテッドXilinx Incorporated 複数のインターポーザを伴うスタックドダイアセンブリ
JP2015056494A (ja) * 2013-09-11 2015-03-23 株式会社東芝 半導体装置および記憶装置
JP2015526905A (ja) * 2012-08-16 2015-09-10 ザイリンクス インコーポレイテッドXilinx Incorporated マルチダイ集積回路に使用するための柔軟なサイズのダイ
JP2015527736A (ja) * 2012-07-23 2015-09-17 マーベル ワールド トレード リミテッド マルチメモリダイを含む半導体パッケージに関連する方法及び配置

Families Citing this family (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4659300B2 (ja) 2000-09-13 2011-03-30 浜松ホトニクス株式会社 レーザ加工方法及び半導体チップの製造方法
TWI326626B (en) 2002-03-12 2010-07-01 Hamamatsu Photonics Kk Laser processing method
JP4358502B2 (ja) * 2002-03-12 2009-11-04 浜松ホトニクス株式会社 半導体基板の切断方法
EP2216128B1 (en) 2002-03-12 2016-01-27 Hamamatsu Photonics K.K. Method of cutting object to be processed
ATE534142T1 (de) 2002-03-12 2011-12-15 Hamamatsu Photonics Kk Verfahren zum auftrennen eines substrats
KR100475716B1 (ko) * 2002-08-13 2005-03-10 매그나칩 반도체 유한회사 복합 반도체 장치의 멀티 반도체 기판의 적층 구조 및 그방법
TWI520269B (zh) 2002-12-03 2016-02-01 Hamamatsu Photonics Kk Cutting method of semiconductor substrate
US6906386B2 (en) * 2002-12-20 2005-06-14 Advanced Analogic Technologies, Inc. Testable electrostatic discharge protection circuits
KR100498488B1 (ko) * 2003-02-20 2005-07-01 삼성전자주식회사 적층형 반도체 패키지 및 그 제조방법
US8685838B2 (en) 2003-03-12 2014-04-01 Hamamatsu Photonics K.K. Laser beam machining method
KR100546698B1 (ko) * 2003-07-04 2006-01-26 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 서브스트레이트
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
TW200511531A (en) * 2003-09-08 2005-03-16 Advanced Semiconductor Eng Package stack module
JP2007066922A (ja) * 2003-11-28 2007-03-15 Renesas Technology Corp 半導体集積回路装置
US8039363B2 (en) * 2003-12-23 2011-10-18 Tessera, Inc. Small chips with fan-out leads
JP2005277338A (ja) * 2004-03-26 2005-10-06 Nec Electronics Corp 半導体装置及びその検査方法
US20060001180A1 (en) * 2004-06-30 2006-01-05 Brian Taggart In-line wire bonding on a package, and method of assembling same
US20070187844A1 (en) 2006-02-10 2007-08-16 Wintec Industries, Inc. Electronic assembly with detachable components
US7928591B2 (en) * 2005-02-11 2011-04-19 Wintec Industries, Inc. Apparatus and method for predetermined component placement to a target platform
KR100761755B1 (ko) * 2005-02-28 2007-09-28 삼성전자주식회사 입출력 비트구조를 조절할 수 있는 반도체 메모리 장치
US20060202317A1 (en) * 2005-03-14 2006-09-14 Farid Barakat Method for MCP packaging for balanced performance
US20060258051A1 (en) * 2005-05-10 2006-11-16 Texas Instruments Incorporated Method and system for solder die attach
JP4276651B2 (ja) * 2005-10-13 2009-06-10 タイコエレクトロニクスアンプ株式会社 Icソケットセット
JP4744269B2 (ja) * 2005-11-02 2011-08-10 パナソニック株式会社 半導体装置とその製造方法
JP4930970B2 (ja) * 2005-11-28 2012-05-16 ルネサスエレクトロニクス株式会社 マルチチップモジュール
JP4708176B2 (ja) * 2005-12-08 2011-06-22 エルピーダメモリ株式会社 半導体装置
US20070152314A1 (en) * 2005-12-30 2007-07-05 Intel Corporation Low stress stacked die packages
US20110222252A1 (en) * 2006-02-10 2011-09-15 Kong-Chen Chen Electronic assembly with detachable components
US20110223695A1 (en) * 2006-02-10 2011-09-15 Kong-Chen Chen Electronic assembly with detachable components
US20110222253A1 (en) * 2006-02-10 2011-09-15 Kong-Chen Chen Electronic assembly with detachable components
US7560798B2 (en) * 2006-02-27 2009-07-14 International Business Machines Corporation High performance tapered varactor
JP4949733B2 (ja) * 2006-05-11 2012-06-13 ルネサスエレクトロニクス株式会社 半導体装置
JP4237207B2 (ja) * 2006-07-07 2009-03-11 エルピーダメモリ株式会社 半導体装置の製造方法
TWI306658B (en) * 2006-08-07 2009-02-21 Chipmos Technologies Inc Leadframe on offset stacked chips package
DE102006045131A1 (de) * 2006-09-25 2008-03-27 Qimonda Ag Die, Die-Anordnung und Verfahren zum Testen eines Dies
KR100843213B1 (ko) * 2006-12-05 2008-07-02 삼성전자주식회사 메모리 칩과 프로세서 칩이 스크라이브 영역에 배열된관통전극을 통해 연결된 다중 입출력 반도체 칩 패키지 및그 제조방법
KR100817091B1 (ko) * 2007-03-02 2008-03-26 삼성전자주식회사 적층형 반도체 패키지 및 그 제조방법
US7705441B2 (en) * 2007-03-06 2010-04-27 Infineon Technologies Ag Semiconductor module
US7663204B2 (en) * 2007-04-27 2010-02-16 Powertech Technology Inc. Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications
US7898813B2 (en) * 2007-06-25 2011-03-01 Kabushiki Kaisha Toshiba Semiconductor memory device and semiconductor memory card using the same
KR100962678B1 (ko) * 2007-07-04 2010-06-11 삼성전자주식회사 듀얼 미러 칩을 포함하는 웨이퍼 및 상기 칩을 포함하는 멀티칩 패키지
US7880309B2 (en) * 2007-07-30 2011-02-01 Qimonda Ag Arrangement of stacked integrated circuit dice having a direct electrical connection
JP5138338B2 (ja) * 2007-11-02 2013-02-06 ルネサスエレクトロニクス株式会社 半導体パッケージ
US8399973B2 (en) * 2007-12-20 2013-03-19 Mosaid Technologies Incorporated Data storage and stackable configurations
KR20090088640A (ko) * 2008-02-15 2009-08-20 삼성전자주식회사 반도체 패키지 제조 방법
US7687921B2 (en) * 2008-05-05 2010-03-30 Super Talent Electronics, Inc. High density memory device manufacturing using isolated step pads
TW200947569A (en) * 2008-05-13 2009-11-16 Richtek Technology Corp Package structure and method
DE102008034918B4 (de) * 2008-07-26 2012-09-27 Feinmetall Gmbh Elektrische Prüfeinrichtung für die Prüfung eines elektrischen Prüflings sowie elektrisches Prüfverfahren
FR2935195B1 (fr) * 2008-08-22 2011-04-29 St Microelectronics Sa Dispositif semi-conducteur a paires de plots
US7925949B2 (en) 2008-10-15 2011-04-12 Micron Technology, Inc. Embedded processor
JP5413829B2 (ja) * 2008-11-10 2014-02-12 サンデン株式会社 インバータ一体型電動圧縮機
JP2010192680A (ja) * 2009-02-18 2010-09-02 Elpida Memory Inc 半導体装置
US9171824B2 (en) 2009-05-26 2015-10-27 Rambus Inc. Stacked semiconductor device assembly
US8174131B2 (en) * 2009-05-27 2012-05-08 Globalfoundries Inc. Semiconductor device having a filled trench structure and methods for fabricating the same
JP5581627B2 (ja) * 2009-08-05 2014-09-03 セイコーエプソン株式会社 集積回路装置及び電子機器
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
TWI481001B (zh) * 2011-09-09 2015-04-11 Dawning Leading Technology Inc 晶片封裝結構及其製造方法
US8704364B2 (en) * 2012-02-08 2014-04-22 Xilinx, Inc. Reducing stress in multi-die integrated circuit structures
US8704384B2 (en) 2012-02-17 2014-04-22 Xilinx, Inc. Stacked die assembly
US20130228867A1 (en) * 2012-03-02 2013-09-05 Kabushiki Kaisha Toshiba Semiconductor device protected from electrostatic discharge
US20130285259A1 (en) * 2012-04-30 2013-10-31 Caleb C. Han Method and system for wafer and strip level batch die attach assembly
US8957512B2 (en) 2012-06-19 2015-02-17 Xilinx, Inc. Oversized interposer
US8869088B1 (en) 2012-06-27 2014-10-21 Xilinx, Inc. Oversized interposer formed from a multi-pattern region mask
TWI469251B (zh) * 2012-08-22 2015-01-11 Realtek Semiconductor Corp 一種電子裝置
CN102832189B (zh) * 2012-09-11 2014-07-16 矽力杰半导体技术(杭州)有限公司 一种多芯片封装结构及其封装方法
JP6207190B2 (ja) * 2013-03-22 2017-10-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9214415B2 (en) * 2013-04-11 2015-12-15 Texas Instruments Incorporated Integrating multi-output power converters having vertically stacked semiconductor chips
JP6242078B2 (ja) * 2013-05-20 2017-12-06 オリンパス株式会社 半導体装置、および半導体装置の位置決め装置
US9547034B2 (en) 2013-07-03 2017-01-17 Xilinx, Inc. Monolithic integrated circuit die having modular die regions stitched together
US9601456B2 (en) * 2014-01-20 2017-03-21 Etron Technology, Inc. System-in-package module and manufacture method for a system-in-package module
US9915869B1 (en) 2014-07-01 2018-03-13 Xilinx, Inc. Single mask set used for interposer fabrication of multiple products
KR102179297B1 (ko) * 2014-07-09 2020-11-18 삼성전자주식회사 모노 패키지 내에서 인터커넥션을 가지는 반도체 장치 및 그에 따른 제조 방법
US10603865B2 (en) * 2014-12-25 2020-03-31 AGC Inc. Insulating member and its attaching method
US20160307873A1 (en) * 2015-04-16 2016-10-20 Mediatek Inc. Bonding pad arrangment design for semiconductor package
US9806088B2 (en) 2016-02-15 2017-10-31 Toshiba Memory Corporation Semiconductor memory device having memory cells arranged three-dimensionally and method of manufacturing the same
US20210351089A1 (en) * 2020-05-11 2021-11-11 Kla Corporation Substrate with Cut Semiconductor Pieces Having Measurement Test Structures for Semiconductor Metrology
KR20220015066A (ko) * 2020-07-30 2022-02-08 삼성전자주식회사 멀티-칩 패키지

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02122559A (ja) * 1988-10-31 1990-05-10 Nec Corp 半導体集積回路のレイアウト方法
JPH08222514A (ja) * 1995-02-17 1996-08-30 Nikon Corp 半導体製造方法
JPH09219419A (ja) * 1996-02-13 1997-08-19 Toshiba Corp 半導体装置およびその製造方法
JPH10144862A (ja) * 1996-11-12 1998-05-29 Nec Kyushu Ltd 半導体集積回路
JPH1131781A (ja) * 1997-05-13 1999-02-02 T I F:Kk メモリモジュールおよびメモリシステム
EP0907207A2 (en) * 1997-08-27 1999-04-07 Nec Corporation Semiconductor device having alternating long and short contact pads with a fine pitch
JPH11168185A (ja) * 1997-12-03 1999-06-22 Rohm Co Ltd 積層基板体および半導体装置
US5949139A (en) * 1997-04-25 1999-09-07 Sharp Kabushiki Kaisha Semiconductor integrated circuit device capable of achieving reductions in chip area and consumption power
WO1999060618A1 (fr) * 1998-05-19 1999-11-25 T.I.F. Co., Ltd. Dispositif a semi-conducteurs et procede de fabrication dudit dispositif
JP2000223651A (ja) * 1999-01-28 2000-08-11 United Microelectronics Corp 対向マルチチップ用パッケージ

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62136844A (ja) * 1985-12-11 1987-06-19 Mitsubishi Electric Corp プロ−ビング装置
JP3104795B2 (ja) 1990-04-26 2000-10-30 株式会社日立製作所 半導体装置及びその製造方法
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
JP2861686B2 (ja) 1992-12-02 1999-02-24 日本電気株式会社 マルチチップモジュール
JP2500643B2 (ja) * 1993-09-27 1996-05-29 日本電気株式会社 半導体装置
US5567653A (en) * 1994-09-14 1996-10-22 International Business Machines Corporation Process for aligning etch masks on an integrated circuit surface using electromagnetic energy
US5640107A (en) * 1995-10-24 1997-06-17 Northrop Grumman Corporation Method for in-circuit programming of a field-programmable gate array configuration memory
US5754405A (en) * 1995-11-20 1998-05-19 Mitsubishi Semiconductor America, Inc. Stacked dual in-line package assembly
US7166495B2 (en) * 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
JP2937132B2 (ja) * 1996-09-02 1999-08-23 日本電気株式会社 半導体装置
US6057598A (en) * 1997-01-31 2000-05-02 Vlsi Technology, Inc. Face on face flip chip integration
JP3304283B2 (ja) 1997-05-22 2002-07-22 シャープ株式会社 半導体集積回路装置
US6208018B1 (en) * 1997-05-29 2001-03-27 Micron Technology, Inc. Piggyback multiple dice assembly
US5877562A (en) * 1997-09-08 1999-03-02 Sur; Harlan Photo alignment structure
JP3938617B2 (ja) * 1997-09-09 2007-06-27 富士通株式会社 半導体装置及び半導体システム
JPH11145403A (ja) 1997-11-04 1999-05-28 Nec Eng Ltd 半導体集積回路
US6043539A (en) * 1997-11-26 2000-03-28 Lsi Logic Corporation Electro-static discharge protection of CMOS integrated circuits
JPH11191575A (ja) * 1997-12-25 1999-07-13 Shinkawa Ltd フリップチップボンディング用部品、フリップチップボンディング確認用部品及びフリップチップボンディング方法
JP3481444B2 (ja) * 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
KR100277438B1 (ko) 1998-05-28 2001-02-01 윤종용 멀티칩패키지
US6157213A (en) * 1998-10-19 2000-12-05 Xilinx, Inc. Layout architecture and method for fabricating PLDs including multiple discrete devices formed on a single chip
JP2000200497A (ja) * 1998-11-05 2000-07-18 Nec Corp ヒュ―ズ判定回路およびメモリの冗長設定回路
US6392304B1 (en) * 1998-11-12 2002-05-21 United Memories, Inc. Multi-chip memory apparatus and associated method
US6081429A (en) * 1999-01-20 2000-06-27 Micron Technology, Inc. Test interposer for use with ball grid array packages assemblies and ball grid array packages including same and methods
US6476499B1 (en) * 1999-02-08 2002-11-05 Rohm Co., Semiconductor chip, chip-on-chip structure device and assembling method thereof
US6376904B1 (en) * 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
JP3737333B2 (ja) * 2000-03-17 2006-01-18 沖電気工業株式会社 半導体装置
JP2001338955A (ja) * 2000-05-29 2001-12-07 Texas Instr Japan Ltd 半導体装置及びその製造方法
US6525413B1 (en) * 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6359340B1 (en) * 2000-07-28 2002-03-19 Advanced Semiconductor Engineering, Inc. Multichip module having a stacked chip arrangement
US6365966B1 (en) * 2000-08-07 2002-04-02 Advanced Semiconductor Engineering, Inc. Stacked chip scale package
KR100385225B1 (ko) * 2001-03-23 2003-05-27 삼성전자주식회사 탐침 패드 및 범프 패드를 갖는 플립 칩형 반도체소자 및 그 제조방법

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02122559A (ja) * 1988-10-31 1990-05-10 Nec Corp 半導体集積回路のレイアウト方法
JPH08222514A (ja) * 1995-02-17 1996-08-30 Nikon Corp 半導体製造方法
JPH09219419A (ja) * 1996-02-13 1997-08-19 Toshiba Corp 半導体装置およびその製造方法
JPH10144862A (ja) * 1996-11-12 1998-05-29 Nec Kyushu Ltd 半導体集積回路
US5949139A (en) * 1997-04-25 1999-09-07 Sharp Kabushiki Kaisha Semiconductor integrated circuit device capable of achieving reductions in chip area and consumption power
JPH1131781A (ja) * 1997-05-13 1999-02-02 T I F:Kk メモリモジュールおよびメモリシステム
EP0907207A2 (en) * 1997-08-27 1999-04-07 Nec Corporation Semiconductor device having alternating long and short contact pads with a fine pitch
JPH11168185A (ja) * 1997-12-03 1999-06-22 Rohm Co Ltd 積層基板体および半導体装置
WO1999060618A1 (fr) * 1998-05-19 1999-11-25 T.I.F. Co., Ltd. Dispositif a semi-conducteurs et procede de fabrication dudit dispositif
JP2000223651A (ja) * 1999-01-28 2000-08-11 United Microelectronics Corp 対向マルチチップ用パッケージ

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7977159B2 (en) 2001-07-10 2011-07-12 Kabushiki Kaisha Toshiba Memory chip and semiconductor device using the memory chip and manufacturing method of those
JP2006013495A (ja) * 2004-06-22 2006-01-12 Samsung Electronics Co Ltd 他のチップを経由して入力信号を伝達する集積回路装置及び集積回路マルチチップパッケージ
US7429794B2 (en) 2004-06-22 2008-09-30 Samsung Electronics Co., Ltd. Multi-chip packaged integrated circuit device for transmitting signals from one chip to another chip
US7466158B2 (en) 2004-10-21 2008-12-16 Elpida Memory, Inc. Multilayer semiconductor device
US7880491B2 (en) 2004-10-21 2011-02-01 Elpida Memory, Inc. Multilayer semiconductor device
JP2006295059A (ja) * 2005-04-14 2006-10-26 Denso Corp 半導体装置およびその製造方法
JP4600130B2 (ja) * 2005-04-14 2010-12-15 株式会社デンソー 半導体装置およびその製造方法
JP2008545255A (ja) * 2005-06-28 2008-12-11 インテル・コーポレーション パッケージング・ロジックおよびメモリ集積回路
JP2007071733A (ja) * 2005-09-07 2007-03-22 Fuji Electric Holdings Co Ltd 光学式絶対値エンコーダ
JP2007158244A (ja) * 2005-12-08 2007-06-21 Fujitsu Ltd 半導体装置に配設される中継部材、半導体装置、及び半導体装置の製造方法
JP4707548B2 (ja) * 2005-12-08 2011-06-22 富士通セミコンダクター株式会社 半導体装置、及び半導体装置の製造方法
JP2008027934A (ja) * 2006-07-18 2008-02-07 Fujitsu Ltd 半導体装置及びその製造方法
JP2012256741A (ja) * 2011-06-09 2012-12-27 Shinko Electric Ind Co Ltd 半導体パッケージ
US9406620B2 (en) 2011-06-09 2016-08-02 Shinko Electric Industries Co., Ltd. Semiconductor package
JP2011249838A (ja) * 2011-08-04 2011-12-08 Renesas Electronics Corp 半導体装置及びその製造方法
JP2015507372A (ja) * 2012-02-08 2015-03-05 ザイリンクス インコーポレイテッドXilinx Incorporated 複数のインターポーザを伴うスタックドダイアセンブリ
JP2015527736A (ja) * 2012-07-23 2015-09-17 マーベル ワールド トレード リミテッド マルチメモリダイを含む半導体パッケージに関連する方法及び配置
JP2015526905A (ja) * 2012-08-16 2015-09-10 ザイリンクス インコーポレイテッドXilinx Incorporated マルチダイ集積回路に使用するための柔軟なサイズのダイ
JP2015056494A (ja) * 2013-09-11 2015-03-23 株式会社東芝 半導体装置および記憶装置

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