WO2002080271A3 - Fluxless flip chip interconnection - Google Patents

Fluxless flip chip interconnection Download PDF

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Publication number
WO2002080271A3
WO2002080271A3 PCT/US2002/005087 US0205087W WO02080271A3 WO 2002080271 A3 WO2002080271 A3 WO 2002080271A3 US 0205087 W US0205087 W US 0205087W WO 02080271 A3 WO02080271 A3 WO 02080271A3
Authority
WO
WIPO (PCT)
Prior art keywords
metal
chip
bumps
substrate
flow temperature
Prior art date
Application number
PCT/US2002/005087
Other languages
French (fr)
Other versions
WO2002080271A2 (en
Inventor
Jiro Kubota
Kenji Takahashi
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to JP2002578572A priority Critical patent/JP2005500672A/en
Priority to EP02713638A priority patent/EP1386356B1/en
Priority to AU2002245476A priority patent/AU2002245476A1/en
Priority to DE60219779T priority patent/DE60219779T2/en
Priority to KR1020037012629A priority patent/KR100555354B1/en
Publication of WO2002080271A2 publication Critical patent/WO2002080271A2/en
Publication of WO2002080271A3 publication Critical patent/WO2002080271A3/en
Priority to HK04104564A priority patent/HK1061741A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L21/603Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
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    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H05K2201/0367Metallic bump or raised conductor not used as solder bump
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    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
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    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3494Heating methods for reflowing of solder
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Abstract

A flip chip method of joining a chip and a substrate is described. A thermocompression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps (305) on the substrate against metal bumps (320) on the chip. The chip is rapidly heated from its non-native side by a pulse heater (415) in the head (410) of the bonder until the re-flow temperature of the solder bumps (305) is reached. Proximate with reaching the re-flow temperature at the solder bumps (305), the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions (320) and joining. Metal caps (330) comprised of a noble metal such as palladium is applied to the surface of the metal bumps (320) to prevent the metal bumps (320) (which generally comprise a highly-conductive and highly-reactive metal such as copper) from oxidizing in the elevated temperatures just prior to and during the re-flow operation.
PCT/US2002/005087 2001-03-28 2002-02-21 Fluxless flip chip interconnection WO2002080271A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2002578572A JP2005500672A (en) 2001-03-28 2002-02-21 Flip-free flip chip interconnect
EP02713638A EP1386356B1 (en) 2001-03-28 2002-02-21 Fluxless flip chip interconnection
AU2002245476A AU2002245476A1 (en) 2001-03-28 2002-02-21 Fluxless flip chip interconnection
DE60219779T DE60219779T2 (en) 2001-03-28 2002-02-21 FLUX-FREE FLIP CHIP CONNECTION
KR1020037012629A KR100555354B1 (en) 2001-03-28 2002-02-21 A method of coupling singulated chip to a substrate package, fluxless flip chip interconnection and a method of forming contact points on chip
HK04104564A HK1061741A1 (en) 2001-03-28 2004-06-25 Fluxless flip chip interconnection

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/821,331 2001-03-28
US09/821,331 US6495397B2 (en) 2001-03-28 2001-03-28 Fluxless flip chip interconnection

Publications (2)

Publication Number Publication Date
WO2002080271A2 WO2002080271A2 (en) 2002-10-10
WO2002080271A3 true WO2002080271A3 (en) 2003-11-27

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Application Number Title Priority Date Filing Date
PCT/US2002/005087 WO2002080271A2 (en) 2001-03-28 2002-02-21 Fluxless flip chip interconnection

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US (1) US6495397B2 (en)
EP (1) EP1386356B1 (en)
JP (1) JP2005500672A (en)
KR (1) KR100555354B1 (en)
CN (1) CN100440496C (en)
AT (1) ATE360888T1 (en)
AU (1) AU2002245476A1 (en)
DE (1) DE60219779T2 (en)
HK (1) HK1061741A1 (en)
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