WO2002078087A3 - Semiconductor chip having multiple conductive layers in an opening, and method for fabricating same - Google Patents

Semiconductor chip having multiple conductive layers in an opening, and method for fabricating same Download PDF

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Publication number
WO2002078087A3
WO2002078087A3 PCT/US2002/005371 US0205371W WO02078087A3 WO 2002078087 A3 WO2002078087 A3 WO 2002078087A3 US 0205371 W US0205371 W US 0205371W WO 02078087 A3 WO02078087 A3 WO 02078087A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
opening
conductive layers
semiconductor chip
multiple conductive
Prior art date
Application number
PCT/US2002/005371
Other languages
French (fr)
Other versions
WO2002078087A2 (en
Inventor
Patrick B Halahan
Oleg Siniaguine
Original Assignee
Tru Si Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tru Si Technologies Inc filed Critical Tru Si Technologies Inc
Priority to KR10-2003-7010999A priority Critical patent/KR100509898B1/en
Priority to EP02739087A priority patent/EP1386355A2/en
Priority to JP2002576018A priority patent/JP4063078B2/en
Priority to AU2002311762A priority patent/AU2002311762A1/en
Publication of WO2002078087A2 publication Critical patent/WO2002078087A2/en
Publication of WO2002078087A3 publication Critical patent/WO2002078087A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H01L2223/6622—Coaxial feed-throughs in active or passive substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Abstract

In some embodiments, a circuit structure comprises a semiconductor substrate (110), an opening (130) passing through the substrate between a first side of the substrate and a second side (110B) of the substrate, and a plurality of conductive layers (210, 320) in the opening. In some embodiments, one conductive layer provides an electromagnetic shield that shields the substrate from AC signals carried by a contact pad (320C) made from another conductive layer on a backside of the substrate. The conductive layers can also be used to form capacitor/rectifier networks. Manufacturing methods are also provided.
PCT/US2002/005371 2001-02-22 2002-02-20 Semiconductor chip having multiple conductive layers in an opening, and method for fabricating same WO2002078087A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR10-2003-7010999A KR100509898B1 (en) 2001-02-22 2002-02-20 Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
EP02739087A EP1386355A2 (en) 2001-02-22 2002-02-20 Semiconductor chip having multiple conductive layers in an opening, and method for fabricating same
JP2002576018A JP4063078B2 (en) 2001-02-22 2002-02-20 Semiconductor structure having a plurality of conductive layers formed in an opening, and a method for manufacturing the same
AU2002311762A AU2002311762A1 (en) 2001-02-22 2002-02-20 Semiconductor chip having multiple conductive layers in an opening, and method for fabricating same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/792,311 US6498381B2 (en) 2001-02-22 2001-02-22 Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
US09/792,311 2001-02-22

Publications (2)

Publication Number Publication Date
WO2002078087A2 WO2002078087A2 (en) 2002-10-03
WO2002078087A3 true WO2002078087A3 (en) 2003-11-20

Family

ID=25156458

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/005371 WO2002078087A2 (en) 2001-02-22 2002-02-20 Semiconductor chip having multiple conductive layers in an opening, and method for fabricating same

Country Status (6)

Country Link
US (3) US6498381B2 (en)
EP (1) EP1386355A2 (en)
JP (1) JP4063078B2 (en)
KR (1) KR100509898B1 (en)
AU (1) AU2002311762A1 (en)
WO (1) WO2002078087A2 (en)

Families Citing this family (132)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020163072A1 (en) * 2001-05-01 2002-11-07 Subhash Gupta Method for bonding wafers to produce stacked integrated circuits
JP3788268B2 (en) * 2001-05-14 2006-06-21 ソニー株式会社 Manufacturing method of semiconductor device
JP4468609B2 (en) * 2001-05-21 2010-05-26 株式会社ルネサステクノロジ Semiconductor device
US7948725B2 (en) * 2001-09-06 2011-05-24 Fuji Electric Systems Co., Ltd. Composite integrated semiconductor device
DE10241086B4 (en) * 2001-09-06 2016-02-18 Fuji Electric Co., Ltd Composite integrated semiconductor device
US20030057544A1 (en) * 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
US20030151132A1 (en) * 2002-02-14 2003-08-14 Crippen Warren Stuart Microelectronic die providing improved heat dissipation, and method of packaging same
US20030153119A1 (en) * 2002-02-14 2003-08-14 Nathan Richard J. Integrated circuit package and method for fabrication
US20060246621A1 (en) * 2002-02-14 2006-11-02 Intel Corporation Microelectronic die including thermally conductive structure in a substrate thereof and method of forming same
JP2003273155A (en) * 2002-03-18 2003-09-26 Fujitsu Ltd Semiconductor device and method of manufacturing the same
JP4110390B2 (en) * 2002-03-19 2008-07-02 セイコーエプソン株式会社 Manufacturing method of semiconductor device
US7026223B2 (en) * 2002-03-28 2006-04-11 M/A-Com, Inc Hermetic electric component package
JP4285629B2 (en) * 2002-04-25 2009-06-24 富士通株式会社 Method for manufacturing interposer substrate mounting integrated circuit
JP4057399B2 (en) * 2002-11-07 2008-03-05 株式会社フジクラ Method for filling metal into fine holes
JP2004228392A (en) * 2003-01-24 2004-08-12 Seiko Epson Corp Manufacturing method of semiconductor device and manufacturing method of semiconductor module
JP2004297019A (en) * 2003-03-28 2004-10-21 Seiko Epson Corp Semiconductor device, circuit board, and electronic apparatus
US6897148B2 (en) 2003-04-09 2005-05-24 Tru-Si Technologies, Inc. Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby
US7098518B1 (en) 2003-08-27 2006-08-29 National Semiconductor Corporation Die-level opto-electronic device and method of making same
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
WO2005031862A1 (en) * 2003-09-26 2005-04-07 Tessera, Inc. Structure and method of making sealed capped chips
US7101792B2 (en) * 2003-10-09 2006-09-05 Micron Technology, Inc. Methods of plating via interconnects
US20050116344A1 (en) * 2003-10-29 2005-06-02 Tessera, Inc. Microelectronic element having trace formed after bond layer
WO2005059961A2 (en) * 2003-12-10 2005-06-30 The Regents Of The University Of California Low crosstalk substrate for mixed-signal integrated circuits
US7060601B2 (en) * 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US7316063B2 (en) * 2004-01-12 2008-01-08 Micron Technology, Inc. Methods of fabricating substrates including at least one conductive via
US7012017B2 (en) * 2004-01-29 2006-03-14 3M Innovative Properties Company Partially etched dielectric film with conductive features
US7282932B2 (en) * 2004-03-02 2007-10-16 Micron Technology, Inc. Compliant contact pin assembly, card system and methods thereof
JP3945493B2 (en) * 2004-04-16 2007-07-18 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof
JP2006019455A (en) 2004-06-30 2006-01-19 Nec Electronics Corp Semiconductor device and manufacturing method thereof
US7866038B2 (en) 2004-07-06 2011-01-11 Tokyo Electron Limited Through substrate, interposer and manufacturing method of through substrate
JP2006024653A (en) * 2004-07-06 2006-01-26 Tokyo Electron Ltd Through substrate and manufacturing method thereof
JP2006024654A (en) * 2004-07-06 2006-01-26 Tokyo Electron Ltd Interposer
US7791141B2 (en) * 2004-07-09 2010-09-07 International Business Machines Corporation Field-enhanced programmable resistance memory cell
KR20070055578A (en) * 2004-08-31 2007-05-30 마쯔시다덴기산교 가부시키가이샤 Micromachine device
SG135065A1 (en) * 2006-02-20 2007-09-28 Micron Technology Inc Conductive vias having two or more elements for providing communication between traces in different substrate planes, semiconductor device assemblies including such vias, and accompanying methods
US7129567B2 (en) * 2004-08-31 2006-10-31 Micron Technology, Inc. Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
US7109068B2 (en) * 2004-08-31 2006-09-19 Micron Technology, Inc. Through-substrate interconnect fabrication methods
US7150516B2 (en) * 2004-09-28 2006-12-19 Hewlett-Packard Development Company, L.P. Integrated circuit and method for manufacturing
EP1691383A1 (en) * 2005-02-14 2006-08-16 TDK Corporation Capacitor, method of making the same, filter using the same, and dielectric thin film used for the same
US20060183270A1 (en) * 2005-02-14 2006-08-17 Tessera, Inc. Tools and methods for forming conductive bumps on microelectronic elements
US8143095B2 (en) 2005-03-22 2012-03-27 Tessera, Inc. Sequential fabrication of vertical conductive interconnects in capped chips
CN101189921A (en) * 2005-06-01 2008-05-28 松下电器产业株式会社 Circuit base plate and its making method and electronic component using the same
US7429529B2 (en) * 2005-08-05 2008-09-30 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
WO2007023950A1 (en) * 2005-08-26 2007-03-01 Hitachi, Ltd. Semiconductor device manufacturing method
US7863187B2 (en) * 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7517798B2 (en) 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
US7633167B2 (en) 2005-09-29 2009-12-15 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US8153464B2 (en) * 2005-10-18 2012-04-10 International Rectifier Corporation Wafer singulation process
US20070138644A1 (en) * 2005-12-15 2007-06-21 Tessera, Inc. Structure and method of making capped chip having discrete article assembled into vertical interconnect
US7936062B2 (en) 2006-01-23 2011-05-03 Tessera Technologies Ireland Limited Wafer level chip packaging
US8394664B2 (en) * 2006-02-02 2013-03-12 William Marsh Rice University Electrical device fabrication from nanotube formations
TW200737506A (en) * 2006-03-07 2007-10-01 Sanyo Electric Co Semiconductor device and manufacturing method of the same
JP2007294652A (en) * 2006-04-25 2007-11-08 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device and method of manufacturing the same
WO2008018524A1 (en) * 2006-08-11 2008-02-14 Sanyo Electric Co., Ltd. Semiconductor device and its manufacturing method
US7829438B2 (en) * 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US7901989B2 (en) * 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US7759166B2 (en) * 2006-10-17 2010-07-20 Tessera, Inc. Microelectronic packages fabricated at the wafer level and methods therefor
JP5010247B2 (en) * 2006-11-20 2012-08-29 オンセミコンダクター・トレーディング・リミテッド Semiconductor device and manufacturing method thereof
US7791199B2 (en) * 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US8569876B2 (en) * 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US20080136038A1 (en) * 2006-12-06 2008-06-12 Sergey Savastiouk Integrated circuits with conductive features in through holes passing through other conductive features and through a semiconductor substrate
US7952195B2 (en) * 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US8604605B2 (en) 2007-01-05 2013-12-10 Invensas Corp. Microelectronic assembly with multi-layer support structure
US7719079B2 (en) * 2007-01-18 2010-05-18 International Business Machines Corporation Chip carrier substrate capacitor and method for fabrication thereof
TW200836322A (en) * 2007-02-16 2008-09-01 Touch Micro System Tech Method of fabricating micro connectors
JP5584474B2 (en) * 2007-03-05 2014-09-03 インヴェンサス・コーポレイション Chip with rear contact connected to front contact by through via
KR100843240B1 (en) * 2007-03-23 2008-07-03 삼성전자주식회사 Semiconductor device for wafer level stack and forming method of through electrode thereof
US7882628B2 (en) * 2007-05-30 2011-02-08 Intel Corporation Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias
US7841080B2 (en) * 2007-05-30 2010-11-30 Intel Corporation Multi-chip packaging using an interposer with through-vias
US7825517B2 (en) * 2007-07-16 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for packaging semiconductor dies having through-silicon vias
KR101458538B1 (en) 2007-07-27 2014-11-07 테세라, 인코포레이티드 A stacked microelectronic unit, and method of fabrication thereof
KR101538648B1 (en) 2007-07-31 2015-07-22 인벤사스 코포레이션 Semiconductor packaging process using through silicon vias
CN101861646B (en) 2007-08-03 2015-03-18 泰塞拉公司 Stack packages using reconstituted wafers
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
JP4961617B2 (en) * 2007-10-01 2012-06-27 新光電気工業株式会社 WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE
US8440917B2 (en) * 2007-11-19 2013-05-14 International Business Machines Corporation Method and apparatus to reduce impedance discontinuity in packages
EP2081224A1 (en) * 2007-12-27 2009-07-22 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Maskless method of preparing metal contacts in a semiconductor substrate for bonding
KR20100126714A (en) * 2008-01-30 2010-12-02 이노벤트 테크놀로지스, 엘엘씨 Method and apparatus for manufacture of via disk
US20090212438A1 (en) * 2008-02-26 2009-08-27 Franz Kreupl Integrated circuit device comprising conductive vias and method of making the same
US9324611B2 (en) * 2008-04-03 2016-04-26 Micron Technology, Inc. Corrosion resistant via connections in semiconductor substrates and methods of making same
US7833895B2 (en) * 2008-05-12 2010-11-16 Texas Instruments Incorporated TSVS having chemically exposed TSV tips for integrated circuit devices
US8680662B2 (en) * 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
JP2010040862A (en) * 2008-08-06 2010-02-18 Fujikura Ltd Semiconductor device
IT1391239B1 (en) * 2008-08-08 2011-12-01 Milano Politecnico METHOD FOR BUMP FORMATION IN SUBSTRATES WITH THROUGH VIA
US8080862B2 (en) * 2008-09-09 2011-12-20 Qualcomm Incorporate Systems and methods for enabling ESD protection on 3-D stacked devices
US8168470B2 (en) 2008-12-08 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound
US8513119B2 (en) 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8093151B2 (en) 2009-03-13 2012-01-10 Stats Chippac, Ltd. Semiconductor die and method of forming noise absorbing regions between THVS in peripheral region of the die
EP2406821A2 (en) * 2009-03-13 2012-01-18 Tessera, Inc. Stacked microelectronic assemblies having vias extending through bond pads
US8263492B2 (en) 2009-04-29 2012-09-11 International Business Machines Corporation Through substrate vias
US8294240B2 (en) * 2009-06-08 2012-10-23 Qualcomm Incorporated Through silicon via with embedded decoupling capacitor
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8558345B2 (en) * 2009-11-09 2013-10-15 International Business Machines Corporation Integrated decoupling capacitor employing conductive through-substrate vias
US8288844B2 (en) * 2009-12-17 2012-10-16 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US9299664B2 (en) * 2010-01-18 2016-03-29 Semiconductor Components Industries, Llc Method of forming an EM protected semiconductor die
CN102148202B (en) * 2010-02-09 2016-06-08 精材科技股份有限公司 Wafer encapsulation body and forming method thereof
JP5609144B2 (en) * 2010-02-19 2014-10-22 ソニー株式会社 Semiconductor device and through electrode test method
JP5115573B2 (en) * 2010-03-03 2013-01-09 オムロン株式会社 Method for manufacturing connection pad
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8492878B2 (en) * 2010-07-21 2013-07-23 International Business Machines Corporation Metal-contamination-free through-substrate via structure
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8502340B2 (en) 2010-12-09 2013-08-06 Tessera, Inc. High density three-dimensional integrated capacitors
US8742541B2 (en) 2010-12-09 2014-06-03 Tessera, Inc. High density three-dimensional integrated capacitors
US9086368B2 (en) * 2011-02-24 2015-07-21 International Business Machines Corporation Non-destructive determination of the moisture content in an electronic circuit board using comparison of capacitance measurements acquired from test coupons, and design structure/process therefor
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
DE102011104305A1 (en) 2011-06-16 2012-12-20 Austriamicrosystems Ag Production method for a semiconductor component with a conductor layer in the semiconductor body and semiconductor component
US8525168B2 (en) * 2011-07-11 2013-09-03 International Business Machines Corporation Integrated circuit (IC) test probe
US8742591B2 (en) 2011-12-21 2014-06-03 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer in notches around conductive TSV for stress relief
US8757897B2 (en) 2012-01-10 2014-06-24 Invensas Corporation Optical interposer
US9323010B2 (en) 2012-01-10 2016-04-26 Invensas Corporation Structures formed using monocrystalline silicon and/or other materials for optical and other applications
JP5880283B2 (en) * 2012-05-29 2016-03-08 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
US8940637B2 (en) * 2012-07-05 2015-01-27 Globalfoundries Singapore Pte. Ltd. Method for forming through silicon via with wafer backside protection
EP2688092A1 (en) * 2012-07-19 2014-01-22 Ipdia Semiconductor die with a through silicon via and corresponding manufacturing process
JP5954058B2 (en) * 2012-09-04 2016-07-20 株式会社デンソー Electronic equipment
US20150050792A1 (en) * 2013-08-13 2015-02-19 Globalfoundries Inc. Extra narrow diffusion break for 3d finfet technologies
JP6286169B2 (en) * 2013-09-26 2018-02-28 新光電気工業株式会社 Wiring board and manufacturing method thereof
US9412806B2 (en) 2014-06-13 2016-08-09 Invensas Corporation Making multilayer 3D capacitors using arrays of upstanding rods or ridges
US9397038B1 (en) 2015-02-27 2016-07-19 Invensas Corporation Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates
US9748106B2 (en) * 2016-01-21 2017-08-29 Micron Technology, Inc. Method for fabricating semiconductor package
US10790426B2 (en) * 2016-04-01 2020-09-29 Nichia Corporation Method of manufacturing light emitting element mounting base member, method of manufacturing light emitting device using the light emitting element mounting base member, light emitting element mounting base member, and light emitting device using the light emitting element mounting base member
JP7160594B2 (en) * 2018-08-09 2022-10-25 太陽誘電株式会社 Capacitor

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5270261A (en) * 1991-09-13 1993-12-14 International Business Machines Corporation Three dimensional multichip package methods of fabrication
US5528080A (en) * 1993-03-05 1996-06-18 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US6002177A (en) * 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6104043A (en) * 1997-01-20 2000-08-15 Abb Research Ltd. Schottky diode of SiC and a method for production thereof
US6122187A (en) * 1998-11-23 2000-09-19 Micron Technology, Inc. Stacked integrated circuits
US6184060B1 (en) * 1996-10-29 2001-02-06 Trusi Technologies Llc Integrated circuits and methods for their fabrication

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL131898C (en) * 1965-03-26
US3508980A (en) * 1967-07-26 1970-04-28 Motorola Inc Method of fabricating an integrated circuit structure with dielectric isolation
JPS5120267B2 (en) * 1972-05-13 1976-06-23
US4353082A (en) * 1977-07-29 1982-10-05 Texas Instruments Incorporated Buried sense line V-groove MOS random access memory
US4580331A (en) * 1981-07-01 1986-04-08 Rockwell International Corporation PNP-type lateral transistor with minimal substrate operation interference and method for producing same
US4694561A (en) * 1984-11-30 1987-09-22 American Telephone And Telegraph Company, At&T Bell Laboratories Method of making high-performance trench capacitors for DRAM cells
US4581814A (en) * 1984-12-13 1986-04-15 At&T Bell Laboratories Process for fabricating dielectrically isolated devices utilizing heating of the polycrystalline support layer to prevent substrate deformation
JPS6269520A (en) * 1985-09-21 1987-03-30 Semiconductor Energy Lab Co Ltd Recess filling method by photo-cvd
US4810669A (en) * 1987-07-07 1989-03-07 Oki Electric Industry Co., Ltd. Method of fabricating a semiconductor device
US5016068A (en) * 1988-04-15 1991-05-14 Texas Instruments Incorporated Vertical floating-gate transistor
US5246877A (en) * 1989-01-31 1993-09-21 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device having a polycrystalline electrode region
US5094972A (en) * 1990-06-14 1992-03-10 National Semiconductor Corp. Means of planarizing integrated circuits with fully recessed isolation dielectric
JP3146316B2 (en) 1991-05-17 2001-03-12 日本テキサス・インスツルメンツ株式会社 Semiconductor device and manufacturing method thereof
US5317432A (en) * 1991-09-04 1994-05-31 Sony Corporation Liquid crystal display device with a capacitor and a thin film transistor in a trench for each pixel
US5332469A (en) * 1992-11-12 1994-07-26 Ford Motor Company Capacitive surface micromachined differential pressure sensor
US5484745A (en) * 1993-10-26 1996-01-16 Yazaki Meter Co., Ltd. Method for forming a semiconductor sensor
US5385861A (en) * 1994-03-15 1995-01-31 National Semiconductor Corporation Planarized trench and field oxide and poly isolation scheme
JPH08201432A (en) * 1995-01-25 1996-08-09 Matsushita Electric Ind Co Ltd Probe sheet and its manufacture
US5854501A (en) * 1995-11-20 1998-12-29 Micron Technology, Inc. Floating gate semiconductor device having a portion formed with a recess
US5747358A (en) * 1996-05-29 1998-05-05 W. L. Gore & Associates, Inc. Method of forming raised metallic contacts on electrical circuits
US6016012A (en) * 1996-11-05 2000-01-18 Cypress Semiconductor Corporation Thin liner layer providing reduced via resistance
US5910687A (en) 1997-01-24 1999-06-08 Chipscale, Inc. Wafer fabrication of die-bottom contacts for electronic devices
US5949030A (en) * 1997-11-14 1999-09-07 International Business Machines Corporation Vias and method for making the same in organic board and chip carriers
US6027956A (en) * 1998-02-05 2000-02-22 Integration Associates, Inc. Process for producing planar dielectrically isolated high speed pin photodiode
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
JP3991300B2 (en) * 2000-04-28 2007-10-17 株式会社Ｓｕｍｃｏ Manufacturing method of bonded dielectric isolation wafer
US6500717B2 (en) * 2000-12-01 2002-12-31 Agere Systems Inc. Method for making an integrated circuit device with dielectrically isolated tubs and related circuit
US20030082847A1 (en) * 2001-10-26 2003-05-01 I-Fire Technologies, Inc. Method and apparatus for wafer thinning
US6794272B2 (en) * 2001-10-26 2004-09-21 Ifire Technologies, Inc. Wafer thinning using magnetic mirror plasma
US6677235B1 (en) * 2001-12-03 2004-01-13 National Semiconductor Corporation Silicon die with metal feed through structure
US6642081B1 (en) * 2002-04-11 2003-11-04 Robert Patti Interlocking conductor method for bonding wafers to produce stacked integrated circuits
JP2004228392A (en) * 2003-01-24 2004-08-12 Seiko Epson Corp Manufacturing method of semiconductor device and manufacturing method of semiconductor module
JP3990347B2 (en) * 2003-12-04 2007-10-10 ローム株式会社 Semiconductor chip, manufacturing method thereof, and semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5270261A (en) * 1991-09-13 1993-12-14 International Business Machines Corporation Three dimensional multichip package methods of fabrication
US5528080A (en) * 1993-03-05 1996-06-18 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US6002177A (en) * 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6184060B1 (en) * 1996-10-29 2001-02-06 Trusi Technologies Llc Integrated circuits and methods for their fabrication
US6104043A (en) * 1997-01-20 2000-08-15 Abb Research Ltd. Schottky diode of SiC and a method for production thereof
US6122187A (en) * 1998-11-23 2000-09-19 Micron Technology, Inc. Stacked integrated circuits

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