WO2002075808A3 - Self-aligned mram contact and method of fabrication - Google Patents

Self-aligned mram contact and method of fabrication Download PDF

Info

Publication number
WO2002075808A3
WO2002075808A3 PCT/US2002/007285 US0207285W WO02075808A3 WO 2002075808 A3 WO2002075808 A3 WO 2002075808A3 US 0207285 W US0207285 W US 0207285W WO 02075808 A3 WO02075808 A3 WO 02075808A3
Authority
WO
WIPO (PCT)
Prior art keywords
self
conductive material
mram
fabrication
aligned
Prior art date
Application number
PCT/US2002/007285
Other languages
French (fr)
Other versions
WO2002075808A2 (en
Inventor
Roger Lee
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to AU2002306683A priority Critical patent/AU2002306683A1/en
Priority to PCT/US2002/007285 priority patent/WO2002075808A2/en
Publication of WO2002075808A2 publication Critical patent/WO2002075808A2/en
Publication of WO2002075808A3 publication Critical patent/WO2002075808A3/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B61/00Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00Galvanomagnetic devices
    • H10N50/01Manufacture or treatment

Abstract

A method of forming self-aligned MRAM contact is disclosed. MRAM stacks including an upper of a conductive material are formed over portions of integraed circuitry. An insulating material is formed over the substrate, including the MRAM stacks with the upper layer of conductive material. The insulating material is subsequently chemically mechanically polished or etched, stopping on the upper layer of conductive material, to expose of the conductive material which are used to self-alinged MRAM contacts.
PCT/US2002/007285 2001-03-15 2002-03-12 Self-aligned mram contact and method of fabrication WO2002075808A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2002306683A AU2002306683A1 (en) 2001-03-15 2002-03-12 Self-aligned mram contact and method of fabrication
PCT/US2002/007285 WO2002075808A2 (en) 2001-03-15 2002-03-12 Self-aligned mram contact and method of fabrication

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/805,915 2001-03-15
US80591501 2001-03-15
PCT/US2002/007285 WO2002075808A2 (en) 2001-03-15 2002-03-12 Self-aligned mram contact and method of fabrication

Publications (2)

Publication Number Publication Date
WO2002075808A2 WO2002075808A2 (en) 2002-09-26
WO2002075808A3 true WO2002075808A3 (en) 2004-02-12

Family

ID=53015433

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/007285 WO2002075808A2 (en) 2001-03-15 2002-03-12 Self-aligned mram contact and method of fabrication

Country Status (2)

Country Link
AU (1) AU2002306683A1 (en)
WO (1) WO2002075808A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841692A (en) * 1996-03-18 1998-11-24 International Business Machines Corporation Magnetic tunnel junction device with antiferromagnetically coupled pinned layer
EP1054449A2 (en) * 1999-05-17 2000-11-22 Motorola, Inc. Magnetic random access memory and fabricating method thereof
US6153443A (en) * 1998-12-21 2000-11-28 Motorola, Inc. Method of fabricating a magnetic random access memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841692A (en) * 1996-03-18 1998-11-24 International Business Machines Corporation Magnetic tunnel junction device with antiferromagnetically coupled pinned layer
US6153443A (en) * 1998-12-21 2000-11-28 Motorola, Inc. Method of fabricating a magnetic random access memory
EP1054449A2 (en) * 1999-05-17 2000-11-22 Motorola, Inc. Magnetic random access memory and fabricating method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HU Y Z ET AL: "Chemical-mechanical polishing as an enabling technology for giant magnetoresistance devices", THIN SOLID FILMS, ELSEVIER-SEQUOIA S.A. LAUSANNE, CH, vol. 308-309, no. 1-4, 31 October 1997 (1997-10-31), pages 555 - 561, XP004110335, ISSN: 0040-6090 *

Also Published As

Publication number Publication date
WO2002075808A2 (en) 2002-09-26
AU2002306683A1 (en) 2002-10-03

Similar Documents

Publication Publication Date Title
WO2005064641A3 (en) Semiconductor device and method of fabricating the same
WO2004055916A3 (en) Phase change memory and manufacturing method therefor
AU2002362009A1 (en) Electrode structure for use in an integrated circuit
WO2002071456A3 (en) Magnetic layer processing
CA2365454A1 (en) Semiconductor photodetection device
WO2006012127A3 (en) Microelectronic packages and methods therefor
EP1612873A4 (en) Collector sheet and electrochemical device
WO2006055179A3 (en) Methods and structures for electrical communication with an overlying electrode for a semiconductor element
WO2002013258A3 (en) Backside contact for integrated circuit and method of forming same
WO2004059751A3 (en) Methods of forming semiconductor mesa structures including self-aligned contact layers and related devices
WO2005001519A3 (en) Embedded waveguide detectors
EP1017096A3 (en) Method of fabricating semiconductor memory device
WO2004077548A3 (en) Connection technology for power semiconductors
SG155041A1 (en) Method of forming contact plug on silicide structure
WO2005050700A3 (en) Line edge roughness reduction for trench etch
TW344125B (en) Semiconductor device and its manufacture
JP2002016157A5 (en)
EP1148543A3 (en) Semiconductor device and process of manufacturing the same
WO2004023533A3 (en) Semiconductor component and method of manufacture
WO2003046974A3 (en) Capacitor and a method for producing a capacitor
WO2001015219A3 (en) Method for producing an integrated circuit having at least one metalicized surface
EP1408724A4 (en) Circuit formed substrate and method of manufacturing circuit formed substrate
TW345743B (en) Method for forming side contact of semiconductor device
TW346668B (en) Contact formation for a semiconductor device
TW200621098A (en) Multi-patterned-layer substrate and manufacturing method thereof

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP