WO2002071611A3 - Monotonic dynamic-static pseudo-nmos logic circuit and method of forming a logic gate array - Google Patents

Monotonic dynamic-static pseudo-nmos logic circuit and method of forming a logic gate array Download PDF

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Publication number
WO2002071611A3
WO2002071611A3 PCT/US2002/003512 US0203512W WO02071611A3 WO 2002071611 A3 WO2002071611 A3 WO 2002071611A3 US 0203512 W US0203512 W US 0203512W WO 02071611 A3 WO02071611 A3 WO 02071611A3
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WO
WIPO (PCT)
Prior art keywords
logic circuit
gate array
clock
forming
nmos
Prior art date
Application number
PCT/US2002/003512
Other languages
French (fr)
Other versions
WO2002071611A2 (en
Inventor
Leonard Forbes
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to DE60239052T priority Critical patent/DE60239052D1/en
Priority to EP02704367A priority patent/EP1378060B1/en
Priority to JP2002570406A priority patent/JP4036096B2/en
Priority to AU2002238056A priority patent/AU2002238056A1/en
Priority to KR1020037010613A priority patent/KR100581010B1/en
Priority to AT02704367T priority patent/ATE497279T1/en
Publication of WO2002071611A2 publication Critical patent/WO2002071611A2/en
Publication of WO2002071611A3 publication Critical patent/WO2002071611A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Abstract

A monotonic dynamic-static pseudo-NMOS logic circuit comprises a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input; and a static logic circuit having a clock bar input and having an output configured to be precharged low when a high value of the complement of the clock signal is provided to the clock bar input. A logic gate array comprises a plurality of vertical ultrathin transistors coupled together.
PCT/US2002/003512 2001-02-15 2002-02-07 Monotonic dynamic-static pseudo-nmos logic circuit and method of forming a logic gate array WO2002071611A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DE60239052T DE60239052D1 (en) 2001-02-15 2002-02-07 MONOTONE DYNAMIC / STATIC PSEUDO-NMOS LOGIC SWITCHING AND METHOD FOR GENERATING A LOGICAL GATE FIELD
EP02704367A EP1378060B1 (en) 2001-02-15 2002-02-07 Monotonic dynamic-static pseudo-nmos logic circuit and method of forming a logic gate array
JP2002570406A JP4036096B2 (en) 2001-02-15 2002-02-07 Monotonic dynamic-static pseudo-NMOS logic circuit and logic gate array forming method
AU2002238056A AU2002238056A1 (en) 2001-02-15 2002-02-07 Monotonic dynamic-static pseudo-nmos logic circuit and method of forming a logic gate array
KR1020037010613A KR100581010B1 (en) 2001-02-15 2002-02-07 Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array
AT02704367T ATE497279T1 (en) 2001-02-15 2002-02-07 MONOTONE DYNAMIC/STATIC PSEUDO-NMOS LOGIC CIRCUIT AND METHOD FOR GENERATING A LOGICAL GATE FIELD

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/788,109 US6649476B2 (en) 2001-02-15 2001-02-15 Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array
US09/788,109 2001-02-15

Publications (2)

Publication Number Publication Date
WO2002071611A2 WO2002071611A2 (en) 2002-09-12
WO2002071611A3 true WO2002071611A3 (en) 2003-10-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/003512 WO2002071611A2 (en) 2001-02-15 2002-02-07 Monotonic dynamic-static pseudo-nmos logic circuit and method of forming a logic gate array

Country Status (9)

Country Link
US (3) US6649476B2 (en)
EP (1) EP1378060B1 (en)
JP (1) JP4036096B2 (en)
KR (1) KR100581010B1 (en)
CN (2) CN1738047B (en)
AT (1) ATE497279T1 (en)
AU (1) AU2002238056A1 (en)
DE (1) DE60239052D1 (en)
WO (1) WO2002071611A2 (en)

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Also Published As

Publication number Publication date
US6649476B2 (en) 2003-11-18
JP2005505150A (en) 2005-02-17
US6801056B2 (en) 2004-10-05
KR100581010B1 (en) 2006-05-16
AU2002238056A1 (en) 2002-09-19
US20030049910A1 (en) 2003-03-13
CN1491483A (en) 2004-04-21
ATE497279T1 (en) 2011-02-15
CN100464502C (en) 2009-02-25
DE60239052D1 (en) 2011-03-10
CN1738047A (en) 2006-02-22
EP1378060B1 (en) 2011-01-26
US20020110032A1 (en) 2002-08-15
US6946879B2 (en) 2005-09-20
EP1378060A2 (en) 2004-01-07
CN1738047B (en) 2010-05-12
US20030153156A1 (en) 2003-08-14
WO2002071611A2 (en) 2002-09-12
JP4036096B2 (en) 2008-01-23
KR20040051575A (en) 2004-06-18

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