WO2002071203A3 - 7 to 3 bit carry-save adder - Google Patents

7 to 3 bit carry-save adder Download PDF

Info

Publication number
WO2002071203A3
WO2002071203A3 PCT/DE2002/000656 DE0200656W WO02071203A3 WO 2002071203 A3 WO2002071203 A3 WO 2002071203A3 DE 0200656 W DE0200656 W DE 0200656W WO 02071203 A3 WO02071203 A3 WO 02071203A3
Authority
WO
WIPO (PCT)
Prior art keywords
save adder
bit carry
significance
bits
adder
Prior art date
Application number
PCT/DE2002/000656
Other languages
German (de)
French (fr)
Other versions
WO2002071203A2 (en
Inventor
Joel Hatsch
Siegmar Koeppe
Eva Lackerschmid
Winfried Kamp
Ronald Kuenemund
Heinz Soeldner
Original Assignee
Infineon Technologies Ag
Joel Hatsch
Siegmar Koeppe
Eva Lackerschmid
Winfried Kamp
Ronald Kuenemund
Heinz Soeldner
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10130484A external-priority patent/DE10130484B4/en
Application filed by Infineon Technologies Ag, Joel Hatsch, Siegmar Koeppe, Eva Lackerschmid, Winfried Kamp, Ronald Kuenemund, Heinz Soeldner filed Critical Infineon Technologies Ag
Publication of WO2002071203A2 publication Critical patent/WO2002071203A2/en
Publication of WO2002071203A3 publication Critical patent/WO2002071203A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/5016—Half or full adders, i.e. basic adder cells for one denomination forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3872—Precharge of output to prevent leakage

Abstract

A carry-save adder for adding up bits having the same significance, comprising seven inputs (i0, i1, ..., i6) receiving seven bits having respectively the same significance w for the addition thereof. w. The adder has an output (s) for a sum bit of significance w, in addition to two outputs (c1, c2) for two transfer bits of significance 2w and 4w.
PCT/DE2002/000656 2001-03-01 2002-02-22 7 to 3 bit carry-save adder WO2002071203A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10109966.5 2001-03-01
DE10109966 2001-03-01
DE10130484A DE10130484B4 (en) 2001-03-01 2001-06-25 7-to-3 bit carry-save adder and adder with it
DE10130484.6 2001-06-25

Publications (2)

Publication Number Publication Date
WO2002071203A2 WO2002071203A2 (en) 2002-09-12
WO2002071203A3 true WO2002071203A3 (en) 2003-04-03

Family

ID=26008658

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/000656 WO2002071203A2 (en) 2001-03-01 2002-02-22 7 to 3 bit carry-save adder

Country Status (1)

Country Link
WO (1) WO2002071203A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3603776A (en) * 1969-01-15 1971-09-07 Ibm Binary batch adder utilizing threshold counters
US3723715A (en) * 1971-08-25 1973-03-27 Ibm Fast modulo threshold operator binary adder for multi-number additions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3603776A (en) * 1969-01-15 1971-09-07 Ibm Binary batch adder utilizing threshold counters
US3723715A (en) * 1971-08-25 1973-03-27 Ibm Fast modulo threshold operator binary adder for multi-number additions

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ETIEMBLE D ET AL: "COMPARISON OF BINARY AND MULTIVALUED ECL ICS FOR IMPLEMENTATION OF THRESHOLD FUNCTIONS", PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON MULTIPLE VALUED LOGIC. BOSTON, MAY 26 - 28, 1987, WASHINGTON, IEEE COMP. SOC. PRESS, US, vol. SYMP. 17, 26 May 1987 (1987-05-26), pages 134 - 141, XP000040445 *
SONG P J ET AL: "CIRCUIT AND ARCHITECTURE TRADE-OFFS FOR HIGH-SPEED MULTIPLICATION", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, vol. 26, no. 9, 1 September 1991 (1991-09-01), pages 1184 - 1198, XP000262814, ISSN: 0018-9200 *

Also Published As

Publication number Publication date
WO2002071203A2 (en) 2002-09-12

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