WO2002060065A1 - An arrangement for trimming an oscillator - Google Patents

An arrangement for trimming an oscillator Download PDF

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Publication number
WO2002060065A1
WO2002060065A1 PCT/SE2002/000082 SE0200082W WO02060065A1 WO 2002060065 A1 WO2002060065 A1 WO 2002060065A1 SE 0200082 W SE0200082 W SE 0200082W WO 02060065 A1 WO02060065 A1 WO 02060065A1
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WO
WIPO (PCT)
Prior art keywords
signal
oscillator
frequency
digital
output
Prior art date
Application number
PCT/SE2002/000082
Other languages
French (fr)
Inventor
Paul Stephansson
Original Assignee
Telefonaktiebolaget Lm Ericsson (Publ)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget Lm Ericsson (Publ) filed Critical Telefonaktiebolaget Lm Ericsson (Publ)
Publication of WO2002060065A1 publication Critical patent/WO2002060065A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/146—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by using digital means for generating the oscillator control signal
    • H03L7/148—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by using digital means for generating the oscillator control signal said digital means comprising a counter or a divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals

Definitions

  • the invention relates generally to oscillators in integrated circuit technology, and more 5 specifically to trimming an oscillator to a desired output frequency.
  • the low power oscillator is controlled by a highly accurate crystal oscillator via a digital-to-analog converter (DAC).
  • DAC digital-to-analog converter
  • the crystal oscillator is not on between messages. Due to variations in temperature and supply voltage, the frequency of the low power oscillator will drift when the crystal oscillator is off. Thus, the low power oscillator has to be trimmed whenever a message is received
  • the oscillation frequency can be adjusted by changing the value of the charging current, the reference voltage level or the capacitance value of the capacitor.
  • a DAC is typically used to set the charging current or the reference voltage level or to adjust the capacitance value using an array of switchable capacitors.
  • the DAC In order to adjust the oscillator frequency with certain accuracy, the DAC must be at least equally accurate. For IC design, a simple DAC is typically limited to an accuracy of 1 % caused by mismatch between components on the chip. It is possible to obtain a better resolution using more sophisticated architectures but they require more power and larger silicon area.
  • the well-defined time resolution is thus used to enhance the resolution of the DAC beyond the limitations caused by mismatch in the components of the DAC.
  • FIG. 1 is a block diagram of an embodiment of an arrangement according to the invention for trimming a relaxation oscillator 1 to provide an output frequency F 0 close to a fixed reference frequency F r .
  • the counter 7 is adapted to generate a digital counter signal K n also comprising N f bits, 5 whose value is incremented by one at each period of the oscillator signal F h .
  • K n also comprising N f bits, 5 whose value is incremented by one at each period of the oscillator signal F h .
  • the output terminal of the comparator 6 is connected to another input terminal of the :0 DAC 5. On its output terminal, the comparator 6 generates a digital signal K x in response to the comparison of the digital fine trim word K f and the digital counter signal K n .
  • the analog coarse trim signal I c and the analog fine trim signal I f are supplied to respective input terminals of an adder 8 to be summed.
  • Fig. 2a shows the output signal K x from the comparator 6.
  • Fig. 2b shows the output signal F h from the oscillator 1.
  • Fig. 2c shows the counter value K n of the counter 7, and
  • Fig. 2d shows the actual output signal F 0 from the divider 2.
  • K x will be one during the first four periods of the twelve periods of the oscillator 1 as illustrated in Fig. 2a. During these first four periods, the oscillator 1 will consequently run at a higher frequency as illustrated in Fig. 2b causing an increase of the average frequency of the oscillator 1.
  • K osc is a gain constant of the oscillator 1 defined by the design of the oscillator 1 and scaled by the reference current I ref of the DAC 5.
  • the average oscillator frequency F h _ avg over M periods is:
  • the oscillator 1 will run at 33 kHz during 4 of the twelve periods and at 30 kHz during 8 5 of the 12 periods.
  • the average frequency will be 31 kHz.
  • the output frequency F 0 becomes 2.583kHz.
  • the step size (21 Hz in our example) is set by accurate time period fractions, not by DAC 5 components.

Abstract

An oscillator (1) is trimmed by a digital-to-analog converter (5) that receives a digital trimming signal in response to difference between a desired frequency and a reference frequency. The oscillator (1) generates a frequency that is M times higher than the desired frequency. A divider (2) divides the oscillator frequency by M to provide the desired frequency. A splitter (4) splits the digital trimming signal into a digital coarse trimming signal, and a digital fine trimming signal. The converter (5) converts the digital coarse trimming signal into an analog coarse trimming signal. A comparator (6) receives the digital fine trimming signal, compares it with a counter signal received from a counter (7) repeatedly counting M periods of the oscillator output signal, and generates an output signal until the value of the digital fine trimming signal and the counter signal are equal. The converter (5) receives said comparator output signal and converts it into an analog fine trimming signal that is added to said analog coarse trimming signal to control the oscillator (1).

Description

AN ARRANGEMENT FOR TRIMMING AN OSCILLATOR
TECHNICAL FIELD
The invention relates generally to oscillators in integrated circuit technology, and more 5 specifically to trimming an oscillator to a desired output frequency.
BACKGROUND OF THE INVENTION
In wireless communication systems of the type in which a radio receiver periodically receives messages, a low power oscillator is used to generate a time reference in the radio
0 receiver. The low power oscillator is controlled by a highly accurate crystal oscillator via a digital-to-analog converter (DAC). In order to save current in the radio, the crystal oscillator is not on between messages. Due to variations in temperature and supply voltage, the frequency of the low power oscillator will drift when the crystal oscillator is off. Thus, the low power oscillator has to be trimmed whenever a message is received
5 and the crystal oscillator is turned on.
When fabricating the radio receiver in integrated circuit (IC) technology, one possible choice for such a low power oscillator is a relaxation oscillator. A relaxation oscillator consumes low current and can be realised without external components. The adjustment !0 accuracy is defined by the mismatching properties of the IC technology used.
In relaxation oscillators, a capacitor is repeatedly charged to a reference voltage level by a charging current and then discharged to zero when a comparator senses that the reference voltage level is reached. The total time of this cycle sets the oscillation !5 frequency assuming that the comparator response time and the capacitor discharge time can be neglected.
The oscillation frequency can be adjusted by changing the value of the charging current, the reference voltage level or the capacitance value of the capacitor. JO Since digital adjustment is desired, a DAC is typically used to set the charging current or the reference voltage level or to adjust the capacitance value using an array of switchable capacitors.
In order to adjust the oscillator frequency with certain accuracy, the DAC must be at least equally accurate. For IC design, a simple DAC is typically limited to an accuracy of 1 % caused by mismatch between components on the chip. It is possible to obtain a better resolution using more sophisticated architectures but they require more power and larger silicon area.
SUMMARY OF THE INVENTION
The object of the invention is to bring about high accuracy frequency adjustment despite mismatch between the components on the chip.
This is attained in accordance with the invention by running an oscillator at a higher frequency than the desired output frequency. Hereby, high resolution in time is obtained as fractions of an output period. To generate the desired output frequency, the oscillator frequency is divided.
The high frequency oscillator uses a DAC for digital control of frequency. The DAC is modified to have an additional least significant bit (LSB) input. By activating this LSB during some of the fractions of an output period, the oscillator runs at a higher frequency during these fractions. This results in a small but well-defined increase in output frequency after the divider.
The well-defined time resolution is thus used to enhance the resolution of the DAC beyond the limitations caused by mismatch in the components of the DAC.
BRIEF DESCRIPTION OF THE DRAWING The invention will be described more in detail below with reference to the appended drawing on which Fig. 1 is a block diagram of an embodiment of an arrangement according to the invention for trimming a current controlled oscillator to a desired frequency, and Figs. 2a-d are diagrams of signals in different nodes of Fig. 1.
DESCRIPTION OF THE INVENTION Fig. 1 is a block diagram of an embodiment of an arrangement according to the invention for trimming a relaxation oscillator 1 to provide an output frequency F0 close to a fixed reference frequency Fr.
In the embodiment in Fig. 1, the relaxation oscillator 1 is current controlled but it is to be understood that it can equally well be controlled by changing a reference voltage or a charging capacitance.
In accordance with the invention, the oscillator 1 is run at a higher frequency Fh than the output frequency F0.
In the embodiment in Fig. 1 , Fh is supposed to equal M x F0, where M is an integer.
To generate the output frequency F0, a frequency divider 2 is connected to the output terminal of the oscillator 1. The divider 2 is adapted to divide the oscillator output frequency Fh by M.
The reference frequency Fr is applied to one input terminal of a control unit 3, while the other input terminal of the control unit 3 is connected to the output terminal of the divider 2. Thus, the other input terminal of the control unit 3 receives the actual output frequency value F0.
The trimming procedure is as follows:
When the radio is powered up, the reference frequency Fr is supplied to the control unit 3. The control unit 3 compares the reference frequency Fr to the actual output frequency F0 received from the output of divider 2. The control unit 3 is adapted to generate a digital control word Kt of Nt bits. The value of Kt corresponds to an optimum value for minimum difference between F0 and Fr. After trimming, Kt is stored to control the oscillator 1 and will not be changed until the next trimming procedure.
The output terminal of the control unit 3 is connected to an input terminal of a splitter 4. The splitter 4 is adapted to split the Nt bits of the control word Kt into a digital coarse trim word Kc comprising Nc bits, and a digital fine trim word Kf comprising Nf bits. The digital coarse trim word Kc is supplied to an input terminal of a DAC 5, and the digital fine trim word Kf is supplied to a (+)-input terminal of a comparator 6.
0
The (-)-input terminal of the comparator 6 is connected to an output terminal of a counter 7 whose input terminal is connected to the output terminal of the oscillator 1.
The counter 7 is adapted to generate a digital counter signal Kn also comprising Nf bits, 5 whose value is incremented by one at each period of the oscillator signal Fh. When the counter 7 has counted to M-l, it restarts and starts at 0 at the next period of the oscillator signal Fh.
The output terminal of the comparator 6 is connected to another input terminal of the :0 DAC 5. On its output terminal, the comparator 6 generates a digital signal Kx in response to the comparison of the digital fine trim word Kf and the digital counter signal Kn.
Kx = 1 if the value of the fine trim word Kf is greater than the value of the counter signal Kn, i.e. if Kf > Kn.
:5
Kx = 0 if Kf ≤ Kn.
In response to the two digital input signals Kc and Kx , the DAC 5 is adapted to generate two output signals namely an analog coarse trim signal Ic = Ir x Kc, and an analog fine 10 trim signal I = Ir x Kx, where Ir is a reference current supplied on a reference input terminal to the DAC 5 in the embodiment in Fig. 1. If = Ir if Kx = l .
If = 0 if Kx = 0.
The average value of If is Ir x Kf/M. The average value of If is the key to enhanced DAC resolution by fractions of time.
The analog coarse trim signal Ic and the analog fine trim signal If are supplied to respective input terminals of an adder 8 to be summed. The adder 8 generates an oscillator trim signal It = Ic + If that is supplied to a control input terminal of the oscillator
I to trim its output frequency Fh.
An example of the operation of the arrangement in Fig. 1 will now be described with reference to Figs. 2a - 2d. Fig. 2a shows the output signal Kx from the comparator 6. Fig. 2b shows the output signal Fh from the oscillator 1. Fig. 2c shows the counter value Kn of the counter 7, and Fig. 2d shows the actual output signal F0 from the divider 2.
Example In the embodiment in Fig. 1, it is supposed that M = 12 and that the splitter 4 generates the digital fine trim word Kf = 4.
This means that the counter 7 will repeatedly generate a signal Kn that increases from 0 to
I I as shown in Fig. 2c, and that the divider 2 will generate an output pulse on every twelfth pulse from the oscillator 1, i.e. at the same time as the counter 7 resets to zero.
With Kf = 4, Kx will be one during the first four periods of the twelve periods of the oscillator 1 as illustrated in Fig. 2a. During these first four periods, the oscillator 1 will consequently run at a higher frequency as illustrated in Fig. 2b causing an increase of the average frequency of the oscillator 1. Assume that the frequency Fh of the oscillator 1 is proportional to the sum of the input signals Kc and Kx to the DAC 5 such that Fh = (Kc+Kx) ■ Kosc where Kosc is a gain constant of the oscillator 1 defined by the design of the oscillator 1 and scaled by the reference current Iref of the DAC 5.
The average oscillator frequency Fh_avg over M periods is:
Figure imgf000007_0001
0 If Kosc = 3 kHz, M=12, and the control unit 3 sets Kc=10 and Kf=4,
F h .avg A 3kHz
12 lO = 31kHz
The oscillator 1 will run at 33 kHz during 4 of the twelve periods and at 30 kHz during 8 5 of the 12 periods. The average frequency will be 31 kHz. After the divider 2, the output frequency F0 becomes 2.583kHz.
If the control unit 3 wants to increase F0 by the least possible amount, it sets Kf=5. During five out of twelve periods, Fh will now run at 33 kHz. The average output :0 frequency Fh_avg = [5x33 kHz + 7x30 kHz]/12 will be 31.25 kHz. After the divider 2, Fo=2.604 kHz.
Thus, the arrangement according to the invention enables F0 to be adjusted in steps of 21 Hz, which is 12 times finer than the resolution of Kosc/M = 250 Hz achieved by only !5 controlling the DAC 5.
Moreover, and most important, the step size (21 Hz in our example) is set by accurate time period fractions, not by DAC 5 components. List of symbols
Figure imgf000008_0001

Claims

CLAIM
An arrangement for finely trimming an oscillator (1) to a desired output frequency, a frequency trim input terminal of the oscillator (1) being connected to an output terminal 5 of a digital-to-analog converter (5), input terminals of the converter (5) being connected to a control circuit (3) generating a digital trimming signal in response to a difference between the desired output frequency and a reference frequency, characterized in
- that the oscillator (1) is adapted to generate a signal whose frequency is M times higher than the desired frequency,
[0 - that a frequency divider (2) is connected to the output of the oscillator (1) for dividing the frequency of its output signal by M to provide a signal with the desired frequency on an output terminal,
- that a trimming signal splitter (4) is adapted to split said digital trimming signal into a digital coarse trimming signal, and a digital fine trimming signal,
[5 - that the converter (5) is adapted to receive said digital coarse trimming signal and convert it into an analog coarse trimming signal,
- that a comparator (6) is adapted to receive said digital fine trimming signal, compare it with a counter signal received from a counter (7) connected with its input terminal to the output terminal of the oscillator (1) to repeatedly count M periods of the oscillator output
>0 signal, and generate an output signal until said digital fine trimming signal and said counter signal are equal, and
- that the converter (5) is adapted to receive said comparator output signal and convert it into an analog fine trimming signal to be added to said analog coarse trimming signal to increase the average frequency of the oscillator (1).
>5
PCT/SE2002/000082 2001-01-26 2002-01-17 An arrangement for trimming an oscillator WO2002060065A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE0100224A SE518287C2 (en) 2001-01-26 2001-01-26 Device for trimming an oscillator
SE0100224-5 2001-01-26

Publications (1)

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WO2002060065A1 true WO2002060065A1 (en) 2002-08-01

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2282719A (en) * 1993-09-13 1995-04-12 Adc Telecommunications Inc Digitally controlled phase locked loop
US5542113A (en) * 1994-09-06 1996-07-30 Motorola, Inc. Carrier derived frequency stabilizer for a radio communication transmitter
US6016080A (en) * 1997-03-30 2000-01-18 Zuta; Marc Computer based fast phase difference measuring unit and PLL using same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2282719A (en) * 1993-09-13 1995-04-12 Adc Telecommunications Inc Digitally controlled phase locked loop
US5542113A (en) * 1994-09-06 1996-07-30 Motorola, Inc. Carrier derived frequency stabilizer for a radio communication transmitter
US6016080A (en) * 1997-03-30 2000-01-18 Zuta; Marc Computer based fast phase difference measuring unit and PLL using same

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TW498601B (en) 2002-08-11
SE0100224L (en) 2002-07-27
SE518287C2 (en) 2002-09-17
SE0100224D0 (en) 2001-01-26

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