WO2002057924A3 - Serial link architecture - Google Patents

Serial link architecture Download PDF

Info

Publication number
WO2002057924A3
WO2002057924A3 PCT/GB2002/000123 GB0200123W WO02057924A3 WO 2002057924 A3 WO2002057924 A3 WO 2002057924A3 GB 0200123 W GB0200123 W GB 0200123W WO 02057924 A3 WO02057924 A3 WO 02057924A3
Authority
WO
WIPO (PCT)
Prior art keywords
serial link
data
pll
fir
chip
Prior art date
Application number
PCT/GB2002/000123
Other languages
French (fr)
Other versions
WO2002057924A2 (en
Inventor
Hayden Clavie Cranford
Vernon Roberts Norman
Martin Leo Schmatz
Original Assignee
Ibm
Ibm Uk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Ibm Uk filed Critical Ibm
Priority to KR10-2003-7009222A priority Critical patent/KR20030078066A/en
Priority to EP02732091A priority patent/EP1354274B1/en
Priority to AU2002219371A priority patent/AU2002219371A1/en
Priority to DE60227048T priority patent/DE60227048D1/en
Publication of WO2002057924A2 publication Critical patent/WO2002057924A2/en
Publication of WO2002057924A3 publication Critical patent/WO2002057924A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H04L2027/0044—Control loops for carrier regulation
    • H04L2027/0063—Elements of loops
    • H04L2027/0067—Phase error detectors

Abstract

A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL) , a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.
PCT/GB2002/000123 2001-01-16 2002-01-15 Serial link architecture WO2002057924A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR10-2003-7009222A KR20030078066A (en) 2001-01-16 2002-01-15 Serial link architecture
EP02732091A EP1354274B1 (en) 2001-01-16 2002-01-15 Serial link architecture
AU2002219371A AU2002219371A1 (en) 2001-01-16 2002-01-15 Serial link architecture
DE60227048T DE60227048D1 (en) 2001-01-16 2002-01-15 SERIAL CONNECTION ARCHITECTURE

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US26240101P 2001-01-16 2001-01-16
US60/262,401 2001-01-16
US09/996,113 US6970529B2 (en) 2001-01-16 2001-11-28 Unified digital architecture
US09/996,113 2001-11-28

Publications (2)

Publication Number Publication Date
WO2002057924A2 WO2002057924A2 (en) 2002-07-25
WO2002057924A3 true WO2002057924A3 (en) 2003-06-26

Family

ID=26949196

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2002/000123 WO2002057924A2 (en) 2001-01-16 2002-01-15 Serial link architecture

Country Status (8)

Country Link
US (2) US6970529B2 (en)
EP (1) EP1354274B1 (en)
KR (1) KR20030078066A (en)
AT (1) ATE398308T1 (en)
AU (1) AU2002219371A1 (en)
DE (1) DE60227048D1 (en)
TW (1) TW571538B (en)
WO (1) WO2002057924A2 (en)

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Also Published As

Publication number Publication date
US20020094055A1 (en) 2002-07-18
WO2002057924A2 (en) 2002-07-25
DE60227048D1 (en) 2008-07-24
US20060029177A1 (en) 2006-02-09
EP1354274A2 (en) 2003-10-22
ATE398308T1 (en) 2008-07-15
US6970529B2 (en) 2005-11-29
TW571538B (en) 2004-01-11
KR20030078066A (en) 2003-10-04
US7646839B2 (en) 2010-01-12
EP1354274B1 (en) 2008-06-11
AU2002219371A1 (en) 2002-07-30

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