WO2002048873A3 - Exception handling in a pipelined processor - Google Patents

Exception handling in a pipelined processor Download PDF

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Publication number
WO2002048873A3
WO2002048873A3 PCT/US2001/047626 US0147626W WO0248873A3 WO 2002048873 A3 WO2002048873 A3 WO 2002048873A3 US 0147626 W US0147626 W US 0147626W WO 0248873 A3 WO0248873 A3 WO 0248873A3
Authority
WO
WIPO (PCT)
Prior art keywords
pipeline
exception
stage
execution
exception handling
Prior art date
Application number
PCT/US2001/047626
Other languages
French (fr)
Other versions
WO2002048873A2 (en
Inventor
Charles P Roth
Ravi P Singh
Gregory A Overkamp
Original Assignee
Intel Corp
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Analog Devices Inc filed Critical Intel Corp
Priority to JP2002550517A priority Critical patent/JP3781419B2/en
Priority to KR1020037007849A priority patent/KR100571322B1/en
Publication of WO2002048873A2 publication Critical patent/WO2002048873A2/en
Publication of WO2002048873A3 publication Critical patent/WO2002048873A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags

Abstract

In one embodiment, a programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The first and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.
PCT/US2001/047626 2000-12-15 2001-12-10 Exception handling in a pipelined processor WO2002048873A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002550517A JP3781419B2 (en) 2000-12-15 2001-12-10 Exception handling in pipelined processors
KR1020037007849A KR100571322B1 (en) 2000-12-15 2001-12-10 Exception handling methods, devices, and systems in pipelined processors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/738,081 2000-12-15
US09/738,081 US6823448B2 (en) 2000-12-15 2000-12-15 Exception handling using an exception pipeline in a pipelined processor

Publications (2)

Publication Number Publication Date
WO2002048873A2 WO2002048873A2 (en) 2002-06-20
WO2002048873A3 true WO2002048873A3 (en) 2002-12-05

Family

ID=24966484

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/047626 WO2002048873A2 (en) 2000-12-15 2001-12-10 Exception handling in a pipelined processor

Country Status (6)

Country Link
US (1) US6823448B2 (en)
JP (1) JP3781419B2 (en)
KR (1) KR100571322B1 (en)
CN (1) CN1269029C (en)
TW (1) TWI223196B (en)
WO (1) WO2002048873A2 (en)

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US8412915B2 (en) 2001-11-30 2013-04-02 Altera Corporation Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
US7215701B2 (en) 2001-12-12 2007-05-08 Sharad Sambhwani Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
US7403981B2 (en) * 2002-01-04 2008-07-22 Quicksilver Technology, Inc. Apparatus and method for adaptive multimedia reception and transmission in communication environments
US6981079B2 (en) * 2002-03-21 2005-12-27 International Business Machines Corporation Critical datapath error handling in a multiprocessor architecture
US7660984B1 (en) 2003-05-13 2010-02-09 Quicksilver Technology Method and system for achieving individualized protected space in an operating system
US7328414B1 (en) 2003-05-13 2008-02-05 Qst Holdings, Llc Method and system for creating and programming an adaptive computing engine
US8108656B2 (en) 2002-08-29 2012-01-31 Qst Holdings, Llc Task definition for specifying resource requirements
US7065665B2 (en) * 2002-10-02 2006-06-20 International Business Machines Corporation Interlocked synchronous pipeline clock gating
US7937591B1 (en) 2002-10-25 2011-05-03 Qst Holdings, Llc Method and system for providing a device which can be adapted on an ongoing basis
US8276135B2 (en) 2002-11-07 2012-09-25 Qst Holdings Llc Profiling of software and circuit designs utilizing data operation analyses
US7225301B2 (en) 2002-11-22 2007-05-29 Quicksilver Technologies External memory controller node
US6856270B1 (en) 2004-01-29 2005-02-15 International Business Machines Corporation Pipeline array
US7386756B2 (en) * 2004-06-17 2008-06-10 Intel Corporation Reducing false error detection in a microprocessor by tracking instructions neutral to errors
US7555703B2 (en) * 2004-06-17 2009-06-30 Intel Corporation Method and apparatus for reducing false error detection in a microprocessor
US7370243B1 (en) * 2004-06-30 2008-05-06 Sun Microsystems, Inc. Precise error handling in a fine grain multithreaded multicore processor
KR100664922B1 (en) * 2004-08-21 2007-01-04 삼성전자주식회사 Method for improving the security of Java
US20060168485A1 (en) * 2005-01-26 2006-07-27 Via Technologies, Inc Updating instruction fault status register
JP5245237B2 (en) * 2006-09-29 2013-07-24 富士通セミコンダクター株式会社 Error handling method
US8359604B2 (en) * 2009-01-22 2013-01-22 Microsoft Corporation Propagating unobserved exceptions in a parallel system
US8688964B2 (en) * 2009-07-20 2014-04-01 Microchip Technology Incorporated Programmable exception processing latency
US8631279B2 (en) 2011-06-07 2014-01-14 Microsoft Corporation Propagating unobserved exceptions in distributed execution environments
CN103294567B (en) * 2013-05-31 2015-10-28 中国航天科技集团公司第九研究院第七七一研究所 A kind of precise abnormal disposal route of single transmit Pyatyi flow water treater
GB2595476B (en) * 2020-05-27 2022-05-25 Graphcore Ltd Exception handling

Citations (2)

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EP0690372A1 (en) * 1993-12-15 1996-01-03 Silicon Graphics, Inc. Superscalar microprocessor instruction pipeline including instruction dispatch and release control

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Patent Citations (2)

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EP0690372A1 (en) * 1993-12-15 1996-01-03 Silicon Graphics, Inc. Superscalar microprocessor instruction pipeline including instruction dispatch and release control

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Also Published As

Publication number Publication date
CN1481529A (en) 2004-03-10
US6823448B2 (en) 2004-11-23
KR100571322B1 (en) 2006-04-17
TWI223196B (en) 2004-11-01
JP3781419B2 (en) 2006-05-31
CN1269029C (en) 2006-08-09
KR20040016829A (en) 2004-02-25
US20020078334A1 (en) 2002-06-20
WO2002048873A2 (en) 2002-06-20
JP2004516546A (en) 2004-06-03

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