WO2002048873A2 - Exception handling in a pipelined processor - Google Patents

Exception handling in a pipelined processor Download PDF

Info

Publication number
WO2002048873A2
WO2002048873A2 PCT/US2001/047626 US0147626W WO0248873A2 WO 2002048873 A2 WO2002048873 A2 WO 2002048873A2 US 0147626 W US0147626 W US 0147626W WO 0248873 A2 WO0248873 A2 WO 0248873A2
Authority
WO
WIPO (PCT)
Prior art keywords
exception
pipeline
stages
execution
instruction
Prior art date
Application number
PCT/US2001/047626
Other languages
French (fr)
Other versions
WO2002048873A3 (en
Inventor
Charles P. Roth
Ravi P. Singh
Gregory A. Overkamp
Original Assignee
Intel Corporation
Analog Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation, Analog Devices, Inc. filed Critical Intel Corporation
Priority to KR1020037007849A priority Critical patent/KR100571322B1/en
Priority to JP2002550517A priority patent/JP3781419B2/en
Publication of WO2002048873A2 publication Critical patent/WO2002048873A2/en
Publication of WO2002048873A3 publication Critical patent/WO2002048873A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags

Definitions

  • This invention relates to exception handling in a processor.
  • a programmable microprocessor such as a digital signal processor, typically includes exception handling hardware for dealing with errors that may be encountered while processing instructions. For example, the processor may encounter illegal instructions (unsupported opcodes), misaligned instructions, instructions that access protected areas of memory, illegal memory addresses, bus errors and the like.
  • the exception handler hardware typically invokes a corresponding software routine, often referred to as an error handler, for responding to the error condition.
  • Figure 1 is a block diagram illustrating an example of a programmable processor configured according to an embodiment of the invention.
  • Figure 2 is a block diagram illustrating an example execution pipeline of the programmable processor.
  • Figure 3 is circuit diagram of an exception pipeline according to an embodiment of the invention.
  • Figure 4 is another circuit diagram of an exception pipeline according the an embodiment of the invention.
  • FIG. 1 is a block diagram illustrating an example of a programmable processor adapted to handle exceptions according to an embodiment of the invention.
  • Processor 2 may include execution pipeline 4, exception pipeline 5 and control unit 6.
  • Execution pipeline 4 may have a number of pipeline stages for concurrently processing more than one instruction. Instructions may be loaded into a first stage of execution pipeline 4 and processed through subsequent stages. Data may pass between the stages in pipelines 4 during a cycle of the system. The results of an instruction may emerge at the end of the pipelines 4 in rapid succession.
  • Control unit 6 may control the flow of instructions and/or data through execution pipeline 4 according to a system clock. For example, during the processing of an instruction, control unit 6 may direct the various components of pipeline 4 to decode an instruction and correctly perform the corresponding operation including, for example, writing the results back to memory.
  • the various stages of execution pipeline 4 may, in the event of an error condition, generate one or more exception signals 17, which may be in the form of an exception code representative of a particular error condition.
  • Exception pipeline 5 may have a number of pipeline stages for receiving the exceptions from execution pipeline 4 and propagating the exceptions in sync with the instructions responsible for causing the error conditions.
  • exception pipeline 5 is ⁇ interlocked" with execution pipeline 4 to ensure that the exceptions flowing through exception pipeline 5 remain synchronized with the instructions flowing through execution pipeline 4. For example, if a stall condition arises in execution pipeline 4, exception pipeline 5 may stall for an equal number of cycles .
  • Figure 2 is a block diagram illustrating an execution pipeline in a programmable processor according to an embodiment of the invention.
  • Control unit 6 may assert control signals 18 to control the flow of instructions and data through execution pipeline 4.
  • Pipeline 4 may have five stages: instruction fetch (IF) , instruction decode (DEC) , address calculation (AC) , execute (EX) and write back (WB) .
  • IF instruction fetch
  • DEC instruction decode
  • AC address calculation
  • EX execute
  • WB write back
  • Instructions may be fetched from a memory device such as, for example, main memory 8 or from an instruction cache during the first stage (IF) by fetch unit 11 and decoded during the second stage (DEC) by instruction decode unit 12.
  • the results are passed to the third stage (AC) , where data address generators 13 may calculate any memory addresses to perform the operation.
  • execution unit 15 may perform one or more operations specified by the instruction such as, for example, adding or multiplying two numbers.
  • Execution unit 15 may contain specialized hardware for performing the operations including, for example, one or more arithmetic logic units (ALU's), floating-point units (FPU) and barrel shifters.
  • ALU's arithmetic logic units
  • FPU floating-point units
  • barrel shifters barrel shifters
  • write back unit 16 may write any results back to data memory or to data registers 14.
  • the stages of pipeline 4 include storage circuits, such as pipeline registers 19, for storing any results of the current stage. Stage registers 19 typically latch the results according to the system clock. Stage registers 19 receive the control signals 18, including one or more stall signals, which control whether or not stage registers 19 latch the results from the previous stage. In this manner, control unit 6 may synchronously stall one or more stages of pipeline 4. As described in detail below, exception pipeline 5 ( Figure 1) also receives control signals 18 and synchronously stalls with execution pipeline 4.
  • the various stages of execution pipeline 4 may generate one or more exception signals (EXPS) indicating an error condition has been detected within the corresponding stage.
  • fetch unit 11 may assert one of the exception signals 17 when a misaligned instruction is encountered.
  • Decode unit 12 may assert an exception signal 17 when an unsupported (illegal) instruction opcode is decoded.
  • Data address generators 13 may assert an exception signal 17 when an illegal memory address is computed.
  • Execution unit 15 may assert an exception signal 17 when an operation results in an error condition, such as an overflow condition.
  • Write back unit 16 may assert an exception signal 17 when an instruction attempts to write results to a protected area of memory.
  • Figure 3 is a block diagram illustrating an example exception pipeline 5 having a plurality of stages .
  • Exception pipeline 5 may have, for example, an instruction fetch (IF) stage, a decode (DEC) stage, an address calculation (AC) stage, an execute (EX) stage and a write back (WB) stage.
  • Each stage of exception pipeline 5 may receive one or more exceptions 17 from a corresponding stage of execution pipeline 4.
  • the IF stage of exception pipeline 5 may receive one or more of M exceptions 17A.
  • Each exception 17 may be represented by an N bit exception code. Therefore, pipeline registers 32 may be capable of storing N bits in parallel.
  • Each stage of exception pipeline 5 includes an exception selection unit 31 for selecting a highest priority exception to be passed to the subsequent stage.
  • instruction fetch selection unit 31A selects one of the M exceptions that may arise in the IF stage of exception pipeline 5.
  • the selected IF exception is stored within stage register 32A upon the next clock cycle.
  • decode selection unit 31B selects either: (1) one of the M exceptions 17B that may arise during the decode stage of execution pipeline 4, or (2) the exception stored within stage register 32A propagated from the IF stage of exception pipeline 5.
  • Decode selection unit 31B stores the selected exception in pipeline stage register 32B.
  • FIG. 4 is a block diagram illustrating a circuit 35 of exception pipeline 5 for controlling the flow of exceptions through the various stages illustrated in Figure
  • circuit 35 propagates one or more exception requests through a series of flip flops 36; the exception requests correspond to the exception codes propagating within exception pipeline 5 of Figure 3.
  • the exception requests are qualified as the propagate through circuit 35 with the same control signals 18 that control the flow of instructions through execution pipeline 4.
  • a first fetch exception signal is qualified with a two signals: (1) a "kill” signal, indicating whether a corresponding instruction is will not be committed in the WB stage due to a change in instruction flow, and (2) a "stall” signal, indicating the corresponding instruction has stalled in execution pipeline
  • circuit 35 The output of flip-flop 36D is again qualified with not stalled and not killed for the write back stage.
  • the output of circuit 35 is an exception_req signal 19 that is received by exception handler 8.
  • exception handler 8 invokes a corresponding exception handling software routine based upon the current exception code 16 supplied by exception pipeline 5 of Figure 3.
  • the input exception signals are pre-qualifled with an instruction valid signal to ensure that the exception is associated with a "valid" instruction, i.e., an instruction that is supported by the instruction set of processor 2.
  • a valid instruction i.e., an instruction that is supported by the instruction set of processor 2.
  • the fetch exception signal is not qualified with a valid instruction signal. This ensures that exceptions arising during the IF stage are correctly serviced regardless of whether valid instructions are fetched.
  • Various embodiments of the invention have been described. For example, a processor having an exception pipeline for propagating exception requests has been described.
  • the processor may be implemented in a variety of systems including general purpose computing systems, digital processing systems, laptop computers, personal digital assistants (PDA's) and cellular phones.
  • the processor may be coupled to a memory device, such as a Flash memory device or a static random access memory (SRAM) , that stores an operating system and other software applications.
  • a memory device such as a Flash memory device or a static random access memory (SRAM) , that stores an operating system and other software applications.

Abstract

In one embodiment, a programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The first and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.

Description

EXCEPTION HANDLING IN A PIPELINED PROCESSOR
BACKGROUND This invention relates to exception handling in a processor.
A programmable microprocessor, such as a digital signal processor, typically includes exception handling hardware for dealing with errors that may be encountered while processing instructions. For example, the processor may encounter illegal instructions (unsupported opcodes), misaligned instructions, instructions that access protected areas of memory, illegal memory addresses, bus errors and the like.
In the event such an error is detected, the exception handler hardware typically invokes a corresponding software routine, often referred to as an error handler, for responding to the error condition.
DESCRIPTION OF DRAWINGS Figure 1 is a block diagram illustrating an example of a programmable processor configured according to an embodiment of the invention. Figure 2 is a block diagram illustrating an example execution pipeline of the programmable processor.
Figure 3 is circuit diagram of an exception pipeline according to an embodiment of the invention.
Figure 4 is another circuit diagram of an exception pipeline according the an embodiment of the invention
DESCRIPTION Figure 1 is a block diagram illustrating an example of a programmable processor adapted to handle exceptions according to an embodiment of the invention. Processor 2 may include execution pipeline 4, exception pipeline 5 and control unit 6.
Execution pipeline 4 may have a number of pipeline stages for concurrently processing more than one instruction. Instructions may be loaded into a first stage of execution pipeline 4 and processed through subsequent stages. Data may pass between the stages in pipelines 4 during a cycle of the system. The results of an instruction may emerge at the end of the pipelines 4 in rapid succession.
Control unit 6 may control the flow of instructions and/or data through execution pipeline 4 according to a system clock. For example, during the processing of an instruction, control unit 6 may direct the various components of pipeline 4 to decode an instruction and correctly perform the corresponding operation including, for example, writing the results back to memory. The various stages of execution pipeline 4 may, in the event of an error condition, generate one or more exception signals 17, which may be in the form of an exception code representative of a particular error condition. Exception pipeline 5 may have a number of pipeline stages for receiving the exceptions from execution pipeline 4 and propagating the exceptions in sync with the instructions responsible for causing the error conditions. As described in detail below, exception pipeline 5 is ^interlocked" with execution pipeline 4 to ensure that the exceptions flowing through exception pipeline 5 remain synchronized with the instructions flowing through execution pipeline 4. For example, if a stall condition arises in execution pipeline 4, exception pipeline 5 may stall for an equal number of cycles .
Figure 2 is a block diagram illustrating an execution pipeline in a programmable processor according to an embodiment of the invention. Control unit 6 may assert control signals 18 to control the flow of instructions and data through execution pipeline 4.
Pipeline 4, for example, may have five stages: instruction fetch (IF) , instruction decode (DEC) , address calculation (AC) , execute (EX) and write back (WB) .
Instructions may be fetched from a memory device such as, for example, main memory 8 or from an instruction cache during the first stage (IF) by fetch unit 11 and decoded during the second stage (DEC) by instruction decode unit 12. At the next clock cycle, the results are passed to the third stage (AC) , where data address generators 13 may calculate any memory addresses to perform the operation. During the execution stage (EX), execution unit 15, may perform one or more operations specified by the instruction such as, for example, adding or multiplying two numbers. Execution unit 15 may contain specialized hardware for performing the operations including, for example, one or more arithmetic logic units (ALU's), floating-point units (FPU) and barrel shifters. A variety of data may be applied to execution unit 15 such as the addresses generated by data address generators 13, data retrieved from memory or data retrieved from data registers 14. During the final stage (WB) , write back unit 16 may write any results back to data memory or to data registers 14.
The stages of pipeline 4 include storage circuits, such as pipeline registers 19, for storing any results of the current stage. Stage registers 19 typically latch the results according to the system clock. Stage registers 19 receive the control signals 18, including one or more stall signals, which control whether or not stage registers 19 latch the results from the previous stage. In this manner, control unit 6 may synchronously stall one or more stages of pipeline 4. As described in detail below, exception pipeline 5 (Figure 1) also receives control signals 18 and synchronously stalls with execution pipeline 4.
The various stages of execution pipeline 4 may generate one or more exception signals (EXPS) indicating an error condition has been detected within the corresponding stage. For example, fetch unit 11 may assert one of the exception signals 17 when a misaligned instruction is encountered. Decode unit 12 may assert an exception signal 17 when an unsupported (illegal) instruction opcode is decoded. Data address generators 13 may assert an exception signal 17 when an illegal memory address is computed. Execution unit 15 may assert an exception signal 17 when an operation results in an error condition, such as an overflow condition. Write back unit 16 may assert an exception signal 17 when an instruction attempts to write results to a protected area of memory. These errors are listed for exemplary purposes only and represent only a subset of errors that may arise during the execution of an instruction.
Figure 3 is a block diagram illustrating an example exception pipeline 5 having a plurality of stages . Exception pipeline 5 may have, for example, an instruction fetch (IF) stage, a decode (DEC) stage, an address calculation (AC) stage, an execute (EX) stage and a write back (WB) stage. Each stage of exception pipeline 5 may receive one or more exceptions 17 from a corresponding stage of execution pipeline 4. For example, the IF stage of exception pipeline 5 may receive one or more of M exceptions 17A. Each exception 17 may be represented by an N bit exception code. Therefore, pipeline registers 32 may be capable of storing N bits in parallel.
Each stage of exception pipeline 5 includes an exception selection unit 31 for selecting a highest priority exception to be passed to the subsequent stage. For example, instruction fetch selection unit 31A selects one of the M exceptions that may arise in the IF stage of exception pipeline 5. The selected IF exception is stored within stage register 32A upon the next clock cycle. Depending on the priority of the various exceptions, decode selection unit 31B selects either: (1) one of the M exceptions 17B that may arise during the decode stage of execution pipeline 4, or (2) the exception stored within stage register 32A propagated from the IF stage of exception pipeline 5. Decode selection unit 31B stores the selected exception in pipeline stage register 32B.
In this manner, exceptions propagate through the various stages of exception pipeline 5 in sync with the various instructions propagating through execution pipeline 4. As an instruction is committed during the write back stage of execution pipeline 4, a corresponding exception may emerge from exception pipeline 5 on the exc_code output, for use by control unit 6 and exception handler 8 invoking a corresponding error handling software routine. In one embodiment, the process of servicing an exception begins several stages before the exception emerges from the WB stage and the appropriate service routine is invoked. Figure 4 is a block diagram illustrating a circuit 35 of exception pipeline 5 for controlling the flow of exceptions through the various stages illustrated in Figure
3. As described in detail below, circuit 35 propagates one or more exception requests through a series of flip flops 36; the exception requests correspond to the exception codes propagating within exception pipeline 5 of Figure 3. The exception requests are qualified as the propagate through circuit 35 with the same control signals 18 that control the flow of instructions through execution pipeline 4. For example, a first fetch exception signal is qualified with a two signals: (1) a "kill" signal, indicating whether a corresponding instruction is will not be committed in the WB stage due to a change in instruction flow, and (2) a "stall" signal, indicating the corresponding instruction has stalled in execution pipeline
4. When these conditions do not exist, the fetch exception signal is latched by flip-flop 36A. In the event of a stall condition, however, the output of flip-flop 36A is fed back and selected by a multiplexer be latched at the following clock cycle. In this manner, the exception requests are interlocked with the instruction flow through execution pipeline 4. Similarly, an exception request generated at the decode stage is ORed with an output of flip-flop 36A to produce a combined decode exception request, which is similarly qualified with the kill and stall condition signals. In this manner, exception request signals may enter circuit 35 at any stage and propagate to flip-flop 36D unless the corresponding instruction is killed within the execution pipeline 4. In this event, the exception request is overwritten and removed from circuit 35.
The output of flip-flop 36D is again qualified with not stalled and not killed for the write back stage. The output of circuit 35 is an exception_req signal 19 that is received by exception handler 8. In response, exception handler 8 invokes a corresponding exception handling software routine based upon the current exception code 16 supplied by exception pipeline 5 of Figure 3.
Although not illustrated in Figure 4, the input exception signals are pre-qualifled with an instruction valid signal to ensure that the exception is associated with a "valid" instruction, i.e., an instruction that is supported by the instruction set of processor 2. Unlike the other exception signals, however, the fetch exception signal is not qualified with a valid instruction signal. This ensures that exceptions arising during the IF stage are correctly serviced regardless of whether valid instructions are fetched. The corresponding instruction as it propagates through execution pipeline 4, however, is marked as an invalid instruction. Various embodiments of the invention have been described. For example, a processor having an exception pipeline for propagating exception requests has been described. The processor may be implemented in a variety of systems including general purpose computing systems, digital processing systems, laptop computers, personal digital assistants (PDA's) and cellular phones. In such a system, the processor may be coupled to a memory device, such as a Flash memory device or a static random access memory (SRAM) , that stores an operating system and other software applications. These and other embodiments are within the scope of the following claims.

Claims

What is claimed is: 1. A method comprising: processing an instruction in a execution pipeline of a programmable processor; and propagating an exception of the instruction through an exception pipeline of the processor.
2. The method of claim 1, processing an instruction in the execution pipeline comprises propagating the instruction through N stages of the execution pipeline, and further wherein propagating the exception status of the instruction in the exception pipeline comprises propagating the exception status of the instruction through N stages of the exception pipeline.
3. The method of claim 1 further comprising receiving the exception from the execution pipeline and storing the exception within the exception pipeline.
4. The method of claim 3, wherein receiving the exception comprises receiving an exception code from one of a plurality of stages of the execution pipeline, and further wherein storing the exception includes storing the exception code within a corresponding stage of the exception pipeline.
5. The method of claim 1 further comprising propagating an exception request bit in the exception pipeline, wherein the exception request bit represents an error condition for an instruction within a corresponding stage of the execution pipeline.
6. The method of claim 1, further comprising stalling the exception pipeline when the execution pipeline is stalled.
7. The method of claim 1, further comprising clearing the exception within the exception pipeline when a corresponding instruction within execution pipeline will not complete execution.
8. The method of claim 4, further comprising servicing the exception when the exception has propagated through a last stage of the exception pipeline.
9. The method of claim 1, wherein propagating the exception through the exception pipeline comprises selecting one of a number of exceptions at stages of the exception pipeline based on a priority associated with the exceptions .
10. The method of claim 1, qualifying the exception at stages of the exception pipeline to ensure the corresponding instruction has not been terminated.
11. The method of claim 1, further comprising qualifying the exception at stages of the exception pipeline, except an instruction fetch stage, to ensure the corresponding instruction is valid.
12. An apparatus comprising: an execution pipeline having a number of stages to execute one or more instructions concurrently; and an exception pipeline having a number of stages to propagate exceptions resulting from the execution of the instructions .
13. The apparatus of claim 12, wherein the execution pipeline and the exception pipeline each have N stages.
14. The apparatus of claim 12, wherein the stages of the exception pipeline include pipeline registers to store exception codes.
15. The apparatus of claim 12, wherein the exception pipeline includes a number of storage circuits to propagate an exception request bit.
16. The apparatus of claim 12, wherein the stages of the exception pipeline and the execution pipeline are controlled by one or more stall signals.
17. The apparatus of claim 15, wherein each stage receives a kill signal to reset the exception request bit.
18. The apparatus of claim 12, further comprising an exception handler receiving the exception request bit from a last stage of the exception pipeline.
19. The apparatus of claim 12, wherein the stages of the exception pipeline include selection logic to select one of a number of exceptions based on a priority associated with the exceptions .
20. The apparatus of claim 12, wherein the stages of the exception pipeline include logic to qualify the exception request bit to ensure the instruction is a valid instruction and has not been terminated.
21. A system comprising: a Flash memory device; and a processor coupled to the Flash memory device, wherein the processor includes an execution pipeline having a number of stages to execute one or more instructions concurrently, and an exception pipeline having a number of stages to propagate exceptions resulting from the execution of the instructions .
22. The system of claim 21, wherein the execution pipeline and the exception pipeline each have N stages.
23. The system of claim 21, wherein the stages of the exception pipeline include pipeline registers to store exception codes
24. The system of claim 21, wherein the exception pipeline includes a number of storage circuits to propagate an exception request bit.
25. The system of claim 21, wherein the stages of the exception pipeline and the execution pipeline are synchronously controlled by one or more stall signals .
26. The system of claim 21, wherein the processor further comprises an exception handler receiving the exception request bit from a last stage of the exception pipeline.
PCT/US2001/047626 2000-12-15 2001-12-10 Exception handling in a pipelined processor WO2002048873A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020037007849A KR100571322B1 (en) 2000-12-15 2001-12-10 Exception handling methods, devices, and systems in pipelined processors
JP2002550517A JP3781419B2 (en) 2000-12-15 2001-12-10 Exception handling in pipelined processors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/738,081 US6823448B2 (en) 2000-12-15 2000-12-15 Exception handling using an exception pipeline in a pipelined processor
US09/738,081 2000-12-15

Publications (2)

Publication Number Publication Date
WO2002048873A2 true WO2002048873A2 (en) 2002-06-20
WO2002048873A3 WO2002048873A3 (en) 2002-12-05

Family

ID=24966484

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/047626 WO2002048873A2 (en) 2000-12-15 2001-12-10 Exception handling in a pipelined processor

Country Status (6)

Country Link
US (1) US6823448B2 (en)
JP (1) JP3781419B2 (en)
KR (1) KR100571322B1 (en)
CN (1) CN1269029C (en)
TW (1) TWI223196B (en)
WO (1) WO2002048873A2 (en)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7962716B2 (en) 2001-03-22 2011-06-14 Qst Holdings, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7249242B2 (en) 2002-10-28 2007-07-24 Nvidia Corporation Input pipeline registers for a node in an adaptive computing engine
US7752419B1 (en) 2001-03-22 2010-07-06 Qst Holdings, Llc Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
US6836839B2 (en) 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7653710B2 (en) 2002-06-25 2010-01-26 Qst Holdings, Llc. Hardware task manager
US6577678B2 (en) 2001-05-08 2003-06-10 Quicksilver Technology Method and system for reconfigurable channel coding
US7046635B2 (en) 2001-11-28 2006-05-16 Quicksilver Technology, Inc. System for authorizing functionality in adaptable hardware devices
US8412915B2 (en) 2001-11-30 2013-04-02 Altera Corporation Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
US6986021B2 (en) 2001-11-30 2006-01-10 Quick Silver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US7215701B2 (en) 2001-12-12 2007-05-08 Sharad Sambhwani Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
US7403981B2 (en) 2002-01-04 2008-07-22 Quicksilver Technology, Inc. Apparatus and method for adaptive multimedia reception and transmission in communication environments
US6981079B2 (en) * 2002-03-21 2005-12-27 International Business Machines Corporation Critical datapath error handling in a multiprocessor architecture
US7660984B1 (en) 2003-05-13 2010-02-09 Quicksilver Technology Method and system for achieving individualized protected space in an operating system
US7328414B1 (en) 2003-05-13 2008-02-05 Qst Holdings, Llc Method and system for creating and programming an adaptive computing engine
US8108656B2 (en) 2002-08-29 2012-01-31 Qst Holdings, Llc Task definition for specifying resource requirements
US7065665B2 (en) * 2002-10-02 2006-06-20 International Business Machines Corporation Interlocked synchronous pipeline clock gating
US7937591B1 (en) 2002-10-25 2011-05-03 Qst Holdings, Llc Method and system for providing a device which can be adapted on an ongoing basis
US8276135B2 (en) 2002-11-07 2012-09-25 Qst Holdings Llc Profiling of software and circuit designs utilizing data operation analyses
US7225301B2 (en) 2002-11-22 2007-05-29 Quicksilver Technologies External memory controller node
US6856270B1 (en) 2004-01-29 2005-02-15 International Business Machines Corporation Pipeline array
US7386756B2 (en) * 2004-06-17 2008-06-10 Intel Corporation Reducing false error detection in a microprocessor by tracking instructions neutral to errors
US7555703B2 (en) * 2004-06-17 2009-06-30 Intel Corporation Method and apparatus for reducing false error detection in a microprocessor
US7370243B1 (en) * 2004-06-30 2008-05-06 Sun Microsystems, Inc. Precise error handling in a fine grain multithreaded multicore processor
KR100664922B1 (en) * 2004-08-21 2007-01-04 삼성전자주식회사 Method for improving the security of Java
US20060168485A1 (en) * 2005-01-26 2006-07-27 Via Technologies, Inc Updating instruction fault status register
JP5245237B2 (en) * 2006-09-29 2013-07-24 富士通セミコンダクター株式会社 Error handling method
US8359604B2 (en) * 2009-01-22 2013-01-22 Microsoft Corporation Propagating unobserved exceptions in a parallel system
US8688964B2 (en) * 2009-07-20 2014-04-01 Microchip Technology Incorporated Programmable exception processing latency
EP2526494B1 (en) 2010-01-21 2020-01-15 SVIRAL, Inc. A method and apparatus for a general-purpose, multiple-core system for implementing stream-based computations
US8631279B2 (en) 2011-06-07 2014-01-14 Microsoft Corporation Propagating unobserved exceptions in distributed execution environments
CN103294567B (en) * 2013-05-31 2015-10-28 中国航天科技集团公司第九研究院第七七一研究所 A kind of precise abnormal disposal route of single transmit Pyatyi flow water treater
GB2595476B (en) * 2020-05-27 2022-05-25 Graphcore Ltd Exception handling

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5297263A (en) * 1987-07-17 1994-03-22 Mitsubishi Denki Kabushiki Kaisha Microprocessor with pipeline system having exception processing features
EP0690372A1 (en) * 1993-12-15 1996-01-03 Silicon Graphics, Inc. Superscalar microprocessor instruction pipeline including instruction dispatch and release control

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5325495A (en) * 1991-06-28 1994-06-28 Digital Equipment Corporation Reducing stall delay in pipelined computer system using queue between pipeline stages
JPH05265739A (en) * 1992-03-16 1993-10-15 Sankyo Seiki Mfg Co Ltd Program changing method for magnetic tape device
US5889982A (en) * 1995-07-01 1999-03-30 Intel Corporation Method and apparatus for generating event handler vectors based on both operating mode and event type
US5603047A (en) * 1995-10-06 1997-02-11 Lsi Logic Corporation Superscalar microprocessor architecture
JP3442225B2 (en) * 1996-07-11 2003-09-02 株式会社日立製作所 Arithmetic processing unit
TW436693B (en) * 1998-08-18 2001-05-28 Ind Tech Res Inst Interrupt control device and method for pipeline processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5297263A (en) * 1987-07-17 1994-03-22 Mitsubishi Denki Kabushiki Kaisha Microprocessor with pipeline system having exception processing features
EP0690372A1 (en) * 1993-12-15 1996-01-03 Silicon Graphics, Inc. Superscalar microprocessor instruction pipeline including instruction dispatch and release control

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"CLOSEST-TO-COMPLETION LOGIC TO STORE FINISHED PROGRAM EXCEPTION CODES" IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 36, no. 4, 1 April 1993 (1993-04-01), pages 87-89, XP000364450 ISSN: 0018-8689 *
DALE S P ET AL: "PIPELINE PROCESSOR EXCEPTION CONTROL MECHANISM" IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 24, no. 11A, April 1982 (1982-04), page 5530 XP000955214 ISSN: 0018-8689 *
GARCIA L C ET AL: "Storage Access-Exception Detection for Pipelined Execution Units" IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 25, no. 12, May 1983 (1983-05), pages 6711-6712, XP002165704 ISSN: 0018-8689 *

Also Published As

Publication number Publication date
US20020078334A1 (en) 2002-06-20
US6823448B2 (en) 2004-11-23
JP3781419B2 (en) 2006-05-31
CN1481529A (en) 2004-03-10
CN1269029C (en) 2006-08-09
KR100571322B1 (en) 2006-04-17
TWI223196B (en) 2004-11-01
WO2002048873A3 (en) 2002-12-05
JP2004516546A (en) 2004-06-03
KR20040016829A (en) 2004-02-25

Similar Documents

Publication Publication Date Title
US6823448B2 (en) Exception handling using an exception pipeline in a pipelined processor
US7028165B2 (en) Processor stalling
KR930004214B1 (en) Data processing system
KR101048234B1 (en) Method and system for combining multiple register units inside a microprocessor
WO2002027475A2 (en) Array processing operations
US7272705B2 (en) Early exception detection
WO2004072848A2 (en) Method and apparatus for hazard detection and management in a pipelined digital processor
US6055628A (en) Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks
US20020103991A1 (en) Multi-cycle instructions
WO2002029557A2 (en) Resetting a programmable processor
US6748523B1 (en) Hardware loops
US6983359B2 (en) Processor and method for pre-fetching out-of-order instructions
JP3822568B2 (en) Event processing
US7065636B2 (en) Hardware loops and pipeline system using advanced generation of loop parameters
WO2002037271A2 (en) Method and apparatus for processing program loops
US6766444B1 (en) Hardware loops
US6983358B2 (en) Method and apparatus for maintaining status coherency between queue-separated functional units
US6442678B1 (en) Method and apparatus for providing data to a processor pipeline
US6920547B2 (en) Register adjustment based on adjustment values determined at multiple stages within a pipeline of a processor
US6308262B1 (en) System and method for efficient processing of instructions using control unit to select operations
US7124285B2 (en) Peak power reduction when updating future file
US20130046961A1 (en) Speculative memory write in a pipelined processor

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CN JP KR SG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): CN JP KR SG

WWE Wipo information: entry into national phase

Ref document number: 1020037007849

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2002550517

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 018207081

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 1020037007849

Country of ref document: KR

WWG Wipo information: grant in national office

Ref document number: 1020037007849

Country of ref document: KR