WO2002047168A3 - Cmos inverter circuits utilizing strained silicon surface channel mosfets - Google Patents

Cmos inverter circuits utilizing strained silicon surface channel mosfets Download PDF

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Publication number
WO2002047168A3
WO2002047168A3 PCT/US2001/046322 US0146322W WO0247168A3 WO 2002047168 A3 WO2002047168 A3 WO 2002047168A3 US 0146322 W US0146322 W US 0146322W WO 0247168 A3 WO0247168 A3 WO 0247168A3
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
cmos inverter
silicon surface
inverter circuits
channel mosfets
Prior art date
Application number
PCT/US2001/046322
Other languages
French (fr)
Other versions
WO2002047168A2 (en
Inventor
Eugene A Fitzgerald
Nicole Gerrisch
Original Assignee
Amberwave Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/884,517 external-priority patent/US20020100942A1/en
Priority claimed from US09/884,172 external-priority patent/US6649480B2/en
Application filed by Amberwave Systems Corp filed Critical Amberwave Systems Corp
Priority to EP01989893A priority Critical patent/EP1399970A2/en
Priority to AU2002228779A priority patent/AU2002228779A1/en
Priority to JP2002548787A priority patent/JP2004523103A/en
Publication of WO2002047168A2 publication Critical patent/WO2002047168A2/en
Publication of WO2002047168A3 publication Critical patent/WO2002047168A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOFSET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
PCT/US2001/046322 2000-12-04 2001-12-04 Cmos inverter circuits utilizing strained silicon surface channel mosfets WO2002047168A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP01989893A EP1399970A2 (en) 2000-12-04 2001-12-04 Cmos inverter circuits utilizing strained silicon surface channel mosfets
AU2002228779A AU2002228779A1 (en) 2000-12-04 2001-12-04 Cmos inverter circuits utilizing strained silicon surface channel mosfets
JP2002548787A JP2004523103A (en) 2000-12-04 2001-12-04 CMOS inverter circuit using strained silicon surface channel MOSFET

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US25098500P 2000-12-04 2000-12-04
US60/250,985 2000-12-04
US09/884,517 US20020100942A1 (en) 2000-12-04 2001-06-19 CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US09/884,517 2001-06-19
US09/884,172 US6649480B2 (en) 2000-12-04 2001-06-19 Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US09/884,172 2001-06-19

Publications (2)

Publication Number Publication Date
WO2002047168A2 WO2002047168A2 (en) 2002-06-13
WO2002047168A3 true WO2002047168A3 (en) 2003-12-31

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/046322 WO2002047168A2 (en) 2000-12-04 2001-12-04 Cmos inverter circuits utilizing strained silicon surface channel mosfets

Country Status (5)

Country Link
US (1) US20020125471A1 (en)
EP (1) EP1399970A2 (en)
JP (1) JP2004523103A (en)
AU (1) AU2002228779A1 (en)
WO (1) WO2002047168A2 (en)

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Also Published As

Publication number Publication date
AU2002228779A1 (en) 2002-06-18
JP2004523103A (en) 2004-07-29
WO2002047168A2 (en) 2002-06-13
US20020125471A1 (en) 2002-09-12
EP1399970A2 (en) 2004-03-24

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