WO2002047148A3 - Electrically isolated via in a multilayer ceramic package - Google Patents

Electrically isolated via in a multilayer ceramic package Download PDF

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Publication number
WO2002047148A3
WO2002047148A3 PCT/US2001/043858 US0143858W WO0247148A3 WO 2002047148 A3 WO2002047148 A3 WO 2002047148A3 US 0143858 W US0143858 W US 0143858W WO 0247148 A3 WO0247148 A3 WO 0247148A3
Authority
WO
WIPO (PCT)
Prior art keywords
multilayer ceramic
ceramic package
electrically isolated
insulator
isolated via
Prior art date
Application number
PCT/US2001/043858
Other languages
French (fr)
Other versions
WO2002047148A2 (en
Inventor
Jeremy W Burdon
Ross A Miesem
Chowdary Ramesh Koripella
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to AU2002225715A priority Critical patent/AU2002225715A1/en
Publication of WO2002047148A2 publication Critical patent/WO2002047148A2/en
Publication of WO2002047148A3 publication Critical patent/WO2002047148A3/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09581—Applying an insulating coating on the walls of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809—Coaxial layout
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49082—Resistor making
    • Y10T29/49083—Heater type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Abstract

A method for forming an electrically isolated via in a multilayer ceramic package and an electrical connection formed within the via are disclosed. The method includes punching a first via (30) in a first layer (10), filling the first via with a cross-linkable paste (40), curing the paste to form an electrical insulator precursor and forming the via in the insulator precursor. The electrical connection formed includes an insulator made from a cross-linked paste supported by a substrate of a multilayer ceramic package and a conductive connection supported by the insulator.
PCT/US2001/043858 2000-12-06 2001-11-19 Electrically isolated via in a multilayer ceramic package WO2002047148A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002225715A AU2002225715A1 (en) 2000-12-06 2001-11-19 Electrically isolated via in a multilayer ceramic package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/730,959 US6629367B2 (en) 2000-12-06 2000-12-06 Electrically isolated via in a multilayer ceramic package
US09/730,959 2000-12-06

Publications (2)

Publication Number Publication Date
WO2002047148A2 WO2002047148A2 (en) 2002-06-13
WO2002047148A3 true WO2002047148A3 (en) 2003-05-15

Family

ID=24937490

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/043858 WO2002047148A2 (en) 2000-12-06 2001-11-19 Electrically isolated via in a multilayer ceramic package

Country Status (4)

Country Link
US (1) US6629367B2 (en)
AU (1) AU2002225715A1 (en)
TW (1) TW510028B (en)
WO (1) WO2002047148A2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6821666B2 (en) * 2001-09-28 2004-11-23 The Regents Of The Univerosity Of California Method of forming a package for mems-based fuel cell
US6608757B1 (en) * 2002-03-18 2003-08-19 International Business Machines Corporation Method for making a printed wiring board
US7387740B2 (en) * 2003-01-17 2008-06-17 Sutech Trading Limited Method of manufacturing metal cover with blind holes therein
US7342308B2 (en) 2005-12-20 2008-03-11 Atmel Corporation Component stacking for integrated circuit electronic package
US7821122B2 (en) * 2005-12-22 2010-10-26 Atmel Corporation Method and system for increasing circuitry interconnection and component capacity in a multi-component package
JP5309013B2 (en) * 2006-03-24 2013-10-09 ウオーターズ・テクノロジーズ・コーポレイシヨン Ceramic-based chromatography apparatus and method for making the same
JP2011049664A (en) * 2009-08-25 2011-03-10 Seiko Instruments Inc Method for manufacturing package, method for manufacturing piezoelectric vibrator, oscillator, electronic device, and radio-controlled timepiece
US8248803B2 (en) * 2010-03-31 2012-08-21 Hong Kong Applied Science and Technology Research Institute Company Limited Semiconductor package and method of manufacturing the same
US8669777B2 (en) * 2010-10-27 2014-03-11 Seagate Technology Llc Assessing connection joint coverage between a device and a printed circuit board
TWI433341B (en) * 2010-12-29 2014-04-01 Au Optronics Corp Method of fabricating a solar cell
US10141353B2 (en) * 2016-05-20 2018-11-27 Qualcomm Incorporated Passive components implemented on a plurality of stacked insulators

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0163368A1 (en) * 1984-03-28 1985-12-04 Plessey Overseas Limited Through hole interconnections
US4571322A (en) * 1982-11-29 1986-02-18 General Electric Company Method for providing insulated holes in conducting substrate
US4715117A (en) * 1985-04-03 1987-12-29 Ibiden Kabushiki Kaisha Ceramic wiring board and its production
US5135595A (en) * 1988-03-11 1992-08-04 International Business Machines Corporation Process for fabricating a low dielectric composite substrate
US5565262A (en) * 1995-01-27 1996-10-15 David Sarnoff Research Center, Inc. Electrical feedthroughs for ceramic circuit board support substrates
WO1999046813A1 (en) * 1998-03-09 1999-09-16 Sarnoff Corporation Method for fabricating double sided ceramic circuit boards using a titanium support substrate

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GB1310880A (en) * 1969-06-13 1973-03-21 Microponent Dev Ltd Multi-layer printed circuit board assemblies
DE2604915C3 (en) * 1976-02-07 1980-03-06 Th. Goldschmidt Ag, 4300 Essen Process for the production of a so-called finished effect film having pores or structures corresponding to the print image
US5013948A (en) 1987-05-04 1991-05-07 Allied-Signal Inc. High power rotating rectifier assembly
US4794048A (en) 1987-05-04 1988-12-27 Allied-Signal Inc. Ceramic coated metal substrates for electronic applications
US4997698A (en) 1987-05-04 1991-03-05 Allied-Signal, Inc. Ceramic coated metal substrates for electronic applications
US5160779A (en) * 1989-11-30 1992-11-03 Hoya Corporation Microprobe provided circuit substrate and method for producing the same
US5034091A (en) 1990-04-27 1991-07-23 Hughes Aircraft Company Method of forming an electrical via structure
US5065227A (en) 1990-06-04 1991-11-12 International Business Machines Corporation Integrated circuit packaging using flexible substrate
JPH0645734A (en) * 1991-03-27 1994-02-18 Nec Corp Printed-wiring board and manufacturing method thereof
JPH04336493A (en) * 1991-05-13 1992-11-24 Fujitsu Ltd Method for forming via conductor of multilayer ceramic substrate
JPH04348595A (en) * 1991-05-27 1992-12-03 Hitachi Ltd Method for repairing multilayer printed circuit board
JPH0590762A (en) * 1991-09-30 1993-04-09 Sharp Corp Manufacture of multilayer printed wiring board
JPH05206641A (en) * 1992-01-29 1993-08-13 Sharp Corp Manufacture of simple through-hole printed wiring board
US5760530A (en) 1992-12-22 1998-06-02 The United States Of America As Represented By The Secretary Of The Air Force Piezoelectric tactile sensor
JPH06302968A (en) * 1993-04-19 1994-10-28 Nippon Cement Co Ltd Multilayer interconnection ceramic board
US5468652A (en) 1993-07-14 1995-11-21 Sandia Corporation Method of making a back contacted solar cell
FR2732467B1 (en) 1995-02-10 1999-09-17 Bosch Gmbh Robert ACCELERATION SENSOR AND METHOD FOR MANUFACTURING SUCH A SENSOR
US5977850A (en) 1997-11-05 1999-11-02 Motorola, Inc. Multilayer ceramic package with center ground via for size reduction
US6000120A (en) 1998-04-16 1999-12-14 Motorola, Inc. Method of making coaxial transmission lines on a printed circuit board

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571322A (en) * 1982-11-29 1986-02-18 General Electric Company Method for providing insulated holes in conducting substrate
EP0163368A1 (en) * 1984-03-28 1985-12-04 Plessey Overseas Limited Through hole interconnections
US4715117A (en) * 1985-04-03 1987-12-29 Ibiden Kabushiki Kaisha Ceramic wiring board and its production
US5135595A (en) * 1988-03-11 1992-08-04 International Business Machines Corporation Process for fabricating a low dielectric composite substrate
US5565262A (en) * 1995-01-27 1996-10-15 David Sarnoff Research Center, Inc. Electrical feedthroughs for ceramic circuit board support substrates
WO1999046813A1 (en) * 1998-03-09 1999-09-16 Sarnoff Corporation Method for fabricating double sided ceramic circuit boards using a titanium support substrate

Also Published As

Publication number Publication date
AU2002225715A1 (en) 2002-06-18
US20020066593A1 (en) 2002-06-06
WO2002047148A2 (en) 2002-06-13
TW510028B (en) 2002-11-11
US6629367B2 (en) 2003-10-07

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