WO2002045157A1 - Simultaneous formation of charge storage and bitline to worldline isolation - Google Patents
Simultaneous formation of charge storage and bitline to worldline isolation Download PDFInfo
- Publication number
- WO2002045157A1 WO2002045157A1 PCT/US2001/024829 US0124829W WO0245157A1 WO 2002045157 A1 WO2002045157 A1 WO 2002045157A1 US 0124829 W US0124829 W US 0124829W WO 0245157 A1 WO0245157 A1 WO 0245157A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- dielectric
- forming
- region
- oxide
- charge trapping
- Prior art date
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/954—Making oxide-nitride-oxide device
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/981—Utilizing varying dielectric thickness
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2001283186A AU2001283186A1 (en) | 2000-11-28 | 2001-08-07 | Simultaneous formation of charge storage and bitline to worldline isolation |
JP2002547222A JP5132024B2 (en) | 2000-11-28 | 2001-08-07 | Method for forming non-volatile semiconductor memory device |
KR1020037007118A KR100810710B1 (en) | 2000-11-28 | 2001-08-07 | Simultaneous formation of charge storage and bitline to worldline isolation |
DE60141035T DE60141035D1 (en) | 2000-11-28 | 2001-08-07 | BITING TO WORDING INSULATION |
EP01961965A EP1338034B1 (en) | 2000-11-28 | 2001-08-07 | Simultaneous formation of charge storage and bitline for wordline isolation |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/723,635 US6465306B1 (en) | 2000-11-28 | 2000-11-28 | Simultaneous formation of charge storage and bitline to wordline isolation |
US09/723,635 | 2000-11-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2002045157A1 true WO2002045157A1 (en) | 2002-06-06 |
Family
ID=24907066
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/024829 WO2002045157A1 (en) | 2000-11-28 | 2001-08-07 | Simultaneous formation of charge storage and bitline to worldline isolation |
Country Status (8)
Country | Link |
---|---|
US (3) | US6465306B1 (en) |
EP (1) | EP1338034B1 (en) |
JP (1) | JP5132024B2 (en) |
KR (1) | KR100810710B1 (en) |
CN (1) | CN100530600C (en) |
AU (1) | AU2001283186A1 (en) |
DE (2) | DE60141035D1 (en) |
WO (1) | WO2002045157A1 (en) |
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- 2001-08-07 EP EP01961965A patent/EP1338034B1/en not_active Expired - Lifetime
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- 2001-08-07 AU AU2001283186A patent/AU2001283186A1/en not_active Abandoned
- 2001-08-07 WO PCT/US2001/024829 patent/WO2002045157A1/en active Application Filing
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US6541816B2 (en) | 2003-04-01 |
EP1338034B1 (en) | 2010-01-06 |
US20020063277A1 (en) | 2002-05-30 |
KR100810710B1 (en) | 2008-03-07 |
US20020192910A1 (en) | 2002-12-19 |
US6555436B2 (en) | 2003-04-29 |
JP2004515076A (en) | 2004-05-20 |
CN1478298A (en) | 2004-02-25 |
CN100530600C (en) | 2009-08-19 |
JP5132024B2 (en) | 2013-01-30 |
EP1338034A1 (en) | 2003-08-27 |
DE60141035D1 (en) | 2010-02-25 |
US6465306B1 (en) | 2002-10-15 |
DE60144340D1 (en) | 2011-05-12 |
KR20030060958A (en) | 2003-07-16 |
AU2001283186A1 (en) | 2002-06-11 |
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