WO2002044699A2 - Verfahren und vorrichtung zur bestimmung von eigenschaften einer integrierten schaltung - Google Patents
Verfahren und vorrichtung zur bestimmung von eigenschaften einer integrierten schaltung Download PDFInfo
- Publication number
- WO2002044699A2 WO2002044699A2 PCT/EP2001/014005 EP0114005W WO0244699A2 WO 2002044699 A2 WO2002044699 A2 WO 2002044699A2 EP 0114005 W EP0114005 W EP 0114005W WO 0244699 A2 WO0244699 A2 WO 0244699A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- image
- resist
- circuit
- design
- simulated image
- Prior art date
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- 0 C1[C@@]2(CC(CC3)**4)C3C4C12 Chemical compound C1[C@@]2(CC(CC3)**4)C3C4C12 0.000 description 2
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/0002—Inspection of images, e.g. flaw detection
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30108—Industrial image inspection
- G06T2207/30148—Semiconductor; IC; Wafer
Definitions
- the present invention relates to a method for determining properties of an integrated circuit according to the preamble of patent claim 1 and a corresponding device according to the preamble of patent claim 10.
- the invention further relates to a corresponding computer program, a corresponding computer program product with program code means and an integrated circuit produced using the method and / or the device according to the invention.
- DRC Design Rule Check
- DRC procedures test the consistency of a design against design rules. In this respect, DRC procedures are useful procedures for checking a structured result. However, DRC methods make no statement as to the extent to which rule violations occur on the printed circuit, caused, for example, by a lack of resolution of the projection device or by the optical proximity effect.
- inspection devices are used as standard for testing masks and the actual circuits printed on silicon wafers.
- the task of the inspection devices is to find defects, for example dust particles.
- Inspection devices of this type are known, for example, from US Pat. No. 5,563,702 and US Pat. No. 5,619,429. Devices of this type generally work according to one of the two methods described below:
- two circuits are compared (die-to-die) by scanning or scanning them against one another with a fine laser beam after careful adjustment of the circuits. If there are any differences between the two circuits, they are then classified and identified as defective. With this method it is not possible to determine systematically caused deviations as these can occur in both circuits.
- the second conventionally used method uses a comparison of the circuit with a database.
- the circuit to be examined is optically scanned, and the signals obtained are compared with a target geometry of a design.
- This method is able to detect defects even when there is no reference object.
- process-related deviations are incorrectly interpreted as defects.
- the inspection devices mentioned are designed to find defects. In principle, you require a functioning process technology.
- the implicit requirement for the implementation of an inspection device of common design is that the geometry of the design is transferred to a silicon wafer without distortion.
- both the mask manufacturing process and the structuring on the silicon wafer by an optical projection apparatus (stepper) are assumed to be ideal.
- stepper optical projection apparatus
- precisely this requirement no longer exists, so that printed circuits deviate more and more from their respective designs. This is due on the one hand to the fact that the optical imaging apparatus acts as a low-pass filter, and on the other hand to the fact that all subsequent process elements, such as photoresists and the etching techniques used, always deliver more distortions.
- a virtual or simulated image of an integrated circuit is obtained, which can be compared with an imaginary or original design of the circuit. According to the invention, it is possible in a simple manner to specify the positions of the (simulated) circuit which deviate from a target by more than a corresponding tolerance value.
- an aerial image and / or a lacquer image and / or an etched image of the circuit is provided as the computationally simulated image.
- the simulated image in particular the lacquer image, is expediently provided assuming a uniform spread of a surface function S (x, y, z), in particular a function describing the spread of a surface in a resist or photoresist to be simulated upon exposure.
- S surface function
- This assumption proves to be very favorable for the implementation of the calculations used in the simulation according to the invention.
- the simulated image particularly the paint image, use an equation of the shape
- the partial differential equation specified here proves to be numerically or analytically solvable, with the analytical solution in particular requiring considerably shorter computation times than conventional methods.
- the assumption is made that ⁇ >> l.
- the partial differential equation for S (x, y, z) m given above can be solved analytically in a particularly simple manner.
- the condition ⁇ »l follows or can be derived from experimental data if ⁇ is regarded as the sensitivity of the resist used.
- the resist profile developed is shown as
- a hierarchically structured data input set describing the design is processed, the simulated image in particular also being provided in the form of a hierarchical structure.
- the computation effort or the computing time can be further shortened compared to conventional methods.
- the device has means for, in particular, automatic change of simulation parameters. With such means it is possible to optimally bring an initially inadequate simulation to convergence.
- FIG. 1 shows, by way of example, details of an integrated circuit in plan view or in perspective view
- FIG. 2 shows a flow chart to illustrate a preferred embodiment of the method according to the invention
- Figure 3 paint images, which is calculated using a conventional full simulation or using the method according to the invention.
- FIG. 4 shows a diagram for comparing the computing time required when using the method according to the invention with the computing time required in conventional methods as a function of the calculated or simulated area.
- Figure 1 shows a section of a design of an integrated circuit.
- the circuit areas are shown in black.
- the corresponding areas are visible in the right-hand illustration as relief-like areas. It is assumed that the right-hand illustration is the associated lacquer structure that was obtained under specific exposure conditions. If you cut the image horizontally at the base of the paint, you get the dotted cut lines of the left representation. The comparison shows that the result of this lithography cut, the so-called lacquer mask, can deviate significantly from the design. Some rule violations are marked by numbers. So 1 denotes a line shortening, 2 indicates line width changes, and 3 indicates corner rounding.
- a design of a circuit is transferred to a mask using a mask writer.
- the mask structure is projected onto a silicon wafer coated with a lacquer and layer structure.
- the image created on the height of the paint surface is referred to as an aerial image.
- the aerial photo describes the three-dimensional intensity distribution of light in the vicinity of the paint surface. It is possible to mathematically simulate the resulting aerial image, taking into account, among other things, projection parameters. Such an exposure of the lacquer or of the resist leads to a photochemical reaction of the exposed parts of the lacquer.
- the aerial image is used to calculate how the optical waves, depending on the lacquer and layer structure, are reflected on the silicon wafer and form standing waves.
- This intensity distribution is used to calculate how the photosensitive component of the lacquer reacts and leads to a new starting component, the concentration map of which is stored in a latent image (lacquer image).
- the tempering of the diffusion of the reaction products is calculated and at the same time the reaction kinetics of the chemical amplification mechanism are calculated.
- the latent image (lacquer image) is developed by wet chemistry, so that a permanent lacquer structure is created.
- This lacquer structure usually serves as a lacquer mask during the following etching. This creates a permanent structure in the silicon (etched image), while all the previous images are fleeting in character. It is also possible to simulate the etching process.
- etching is mostly carried out as reactive ion etching.
- the inspection of an integrated or printed circuit with regard to existing rule violations can be achieved according to the invention in that the design, described by a set of geometry ⁇ G ⁇ or by an optical proximity ty effect corrected geometry amount ⁇ G 1 ⁇ is introduced into a simulation device which calculates a geometry amount ⁇ G 11 ⁇ which corresponds to selectable views of the integrated circuit.
- the simulation device uses different models for the process steps and the associated parameters. Possible views are, for example, the aerial images, lacquer images or etched images already mentioned.
- the comparison for correctness: the simulated or calculated integrated circuit can be achieved according to the invention by comparing the amount of geometry ⁇ G2 ' ⁇ with the originally intended design ⁇ G ⁇ .
- the contour lines m of the quantity ⁇ G2 ' ⁇ ZU are calculated and to compare them with the design ⁇ G ⁇ . It is important in the comparison that, if a proximity correction has been carried out, the comparison is made against the quantity ⁇ G ⁇ and not against the input data ⁇ G 1 ⁇ .
- a set of design rules can also be used instead of the set ⁇ G ⁇ .
- the design rules are expanded to include process rules that must also be fulfilled. For this, for example, the rule pays that the depth of field in the lithography process must not be less than a minimum. If rule violations occur, they are expediently logged and output in a list.
- the result of the comparison can be specified in a list of rule violations.
- the process parameters can be modified using an optimizer so that a modified simulation can be carried out. This possibility is shown schematically in Figure 2.
- the invention aims to accelerate the simulation by calculating at least one of the individual steps of the simulation by means of a suitable fast algorithm.
- a quick aerial image calculation and / or a fast lacquer image calculation and / or a fast etch image calculation are desired.
- the invention provides analytical solutions or approximations which are orders of magnitude faster than previously non-analytical (ie numerical) methods.
- a method for the rapid calculation of a paint image ie simulation of a development process
- the lacquer surface (for example during development) spreads in all directions. This means that a lacquer area that has changed chemically or has been chemically changed due to the exposure expands in all directions.
- the lacquer surface first spreads in one direction (for example perpendicular to the lacquer surface) and then in a direction perpendicular thereto (for example parallel to the lacquer surface).
- the assumption according to the invention of the spread of the paint surface in all directions leads to a simplification of the algorithms, as will be explained in more detail below. It should be noted that the speed of the propagation depends on the contrast of the resist used and the (x, y, z) distribution of the intensity in the resist.
- the speed of the spreading of the lacquer surface can be Describe dependence on an (x, y) distribution of intensity. With x and y, linearly independent directions parallel to the paint surface are designated.
- FIG. 3 Simulations of horizontal sections through the photoresist after development are shown here.
- the left image was created by a complete numerical simulation, the right one by the fast approximation proposed according to the invention using the assumptions described above.
- the time advantage and therefore the area gain is about two orders of magnitude.
- Figure 4 For conventional methods (dotted line) and the fast approximation according to the invention (solid line), the required computing time is shown as a function of the area.
- the logarithmic Y axis shows that the speed increase is about two orders of magnitude.
- the spread of a contour profile can be described in the context of a stationary level set formulation. It is initially assumed that there is a two-dimensional case in which the surface or the spreading contour profile is a spreading curve. First the evolving or spreading zero level set is created above the X-Y level. Let S (x, y, z) be the development time t at which the curve crosses the point (x, y, z). The surface S (x, y, z) in this case fulfills the equation introduced by Osher and Sethian (J.A. Sethian, Level Set Methods, University of California, Berkeley, 1996)
- r is the speed function or a function describing the development rate of the resist.
- the position of the front T is defined by the level set of the time of the function S (x, y, z), whereby one
- the shape of the final resist profile can be calculated from equations (1) and (2), the speed function being expediently defined as the development rate function, which defines the development rate r (x, y, z) as a function of the intensity I (x, y) , z) describes the aerial photo .
- ⁇ is the dose given in large, uncovered or free areas of the resist or the resist surface
- ⁇ 0 is a threshold dose (in particular for triggering a development of the resist)
- ⁇ a non-linearity parameter or sensitivity parameter which describes the non-linearity or sensitivity of the resist or the resist development process.
- equation (5) in the one-dimensional case reduces to the equation given by Mack in "Enhanced Lumped Parameter Model for Photolithography, SPIE, Vol. 2197/501, 1994” if the absorption coefficient is neglected.
- Equation (5) can also be extended to the three-dimensional case. Overall, you get the equation
- equation (6) can be represented as
- equation (6) describing the resist profile S (x, y, z) can be solved analytically in a simple manner, whereby, as already mentioned, it is assumed that ⁇ is the sensitivity of the represents photoresists used, ⁇ can be described in a manner known per se by considering the relationship between the dose of the light acting on the resist and the depth of the resist (viewed starting from the resist surface).
- Equation (11) represents the general solution of equation (6). If one now starts from an intensity I (x, y, z) as described in equation (7), one obtains from equations (11) and (12) the following equation for the developed resist profile:
- F (x, y) can be represented in the form
- d is the resist thickness
- D ff is the effective resist thickness mentioned above
- ⁇ is the absorption coefficient of the resist
- the resist profile calculated or simulated in this way depends on the intensity of the aerial image I (x, y).
- a very simple analytical relationship is obtained for defining or representing a resist profile without the need to introduce or consider chemical parameters.
- the method presented is based solely on physical concepts and parameters and allows a resist profile for large areas to be calculated very quickly.
- the model presented is two orders of magnitude faster than conventional full simulations of a resist profile, which are based on chemical concepts.
- Equations (6) or (9) can be solved analytically or numerically, the two types of solution can be processed much faster and more effectively using conventionally used models or algorithms.
- equation (2) it is possible to formulate a stationary level set equation, the position of the front T being given by the level set of the value t of the function S (x, y, z), as follows from equation (2).
- p (x, y, t) 0 ⁇ .
- the simulation can be further accelerated by using a hierarchy present in the design.
- the hierarchy existing in the design can be exploited by working through the hierarchy tree from bottom to top in a suitable manner, sheet by sheet, while ensuring continuity at the sheet margins. In this way, depending on the level of hierarchy, the computing time can be reduced by several orders of magnitude.
- Hierarchical processing An essential idea in hierarchical processing is to work on the hierarchy tree itself instead of an expanded, flat design. If the design contains many repeating structures, only the different types are saved instead of the many individual structures. At the point of their occurrence, a pointer points to the respective structure.
- a main problem of hierarchical processing is to ensure continuity at the borders of the cells (or sheets). According to the method now proposed, this is done by surrounding each cell with a hem before the actual data processing, which corresponds to the range of the corresponding physical effects that are currently being processed or must be taken into account.
- n is the number of all elements in the flat design
- n SVar is the corresponding amount in the tree or a branch of the tree.
- PHF is greater than or equal to 1.
- the comparison of the geometry quantities ⁇ G 11 ⁇ with ⁇ G ⁇ or ⁇ G ' ⁇ mentioned above requires, for example, a distance calculation within a figure along the curved contour lines and a comparison with a straight line nominal geometry.
- a distance calculation from neighbor to neighbor along curved contour lines and comparison with a linear nominal geometry must also be carried out.
- these calculations are also carried out on a hierarchical amount of data. This means that the computing time can be significantly reduced again, or the usable area increased.
- the comparison result is expediently specified in a coordinate list with the actual and target value of the distance.
- the lists are sorted according to various aspects in order to identify possible common causes of the injuries. Frequency distributions are created on the (x, y) level, grouped for example by cells or figure type, e.g. B. single lines, webs and ditches, or contact holes.
- the rule violations can be minimized by repeatedly carrying out the inspection process after specific changes to the process conditions have been made or set.
- the system uses the steepest gradient method to determine the parameter changes that bring about the most improvement.
- semi-automatic operation is provided, in which the user triggers the repetition of the process.
- the optimization is carried out automatically until the process has converged.
- the termination criteria can be selected by the user from a certain supply.
- the proposed way according to the invention is therefore to generate the possible different neighborhoods for each cell and to store them in a new hierarchy tree.
- Such variants of the cells are called tiles.
- Each tile is therefore surrounded by a border that corresponds to the width of the sphere of influence of the neighboring cells on a cell in question. speaks .
- the resulting tree is usually less compact than the original one, but it is the most compact description of the hierarchy tree in case you take note of the underlying physical effects, which of course do not stop at cell boundaries.
- the calculation of the aerial photo is an example.
- the tiles are generated, the area of influence in this case being given by the range of the optical interferences.
- the range e.g. B. specifies that the intensity of the secondary maxima - below a threshold of z. B. 1% has fallen.
- a range of n- ⁇ / Na is selected, where n is in the region of 10.
- the list of violations of rules obtained when comparing a simulated image with the original design can be used to perform an optimization.
- Previous algorithms for the steps of image creation, image transfer and structure transfer cannot be formulated analytically.
- the user can, for example, manually select a set of parameters that should be lubricated.
- the method according to the invention is non-iterative here, provided the derivative is linear. If it is iterative, it has a much faster convergence behavior than conventional methods or algorithms.
- the optimization runs independently. For this purpose, all derivations are formed at the locations of maximum rule violations and then the parameters that cause particularly strong changes are filtered out.
- the method proposed according to the invention is thus identical to the above-mentioned inspection method "die-to-database".
- the invention does not reveal any defects in an actual circuit or a mask, but rather the system-related deviations in the technology processes, as well as weaknesses in the design or in the design modified by proximity correction.
- it is possible in a simple manner, among other things, to automatically filter out the weak points from the calculated images and to store them in a list.
- the invention proves to be particularly advantageous to be able to determine the distances of objects in the context of the simulated circuit (or to compare them with the circuit design) on each image plane.
- This has the advantage of the step-by-step approach when implementing the algorithm shown.
- the analysis can be carried out at the level of the aerial image, the lacquer image or latent image or the etched image or structural image.
- the distance calculation is expediently carried out in two stages. First the interior of the figure is run through and it is checked whether the widths are within a predetermined range (usually ⁇ 10%). The distances between the figures are then calculated, again paying attention to the design rules and / or the comparison with the original design.
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/433,250 US7302090B2 (en) | 2000-11-30 | 2001-11-30 | Method and device for determining the properties of an integrated circuit |
JP2002546194A JP4216592B2 (ja) | 2000-11-30 | 2001-11-30 | 集積回路の特性を測定するプロセスと装置 |
AU2002227965A AU2002227965A1 (en) | 2000-11-30 | 2001-11-30 | Method and device for determining the properties of an integrated circuit |
KR1020037007344A KR100846018B1 (ko) | 2000-11-30 | 2001-11-30 | 집적 회로의 특성 측정 장치 및 방법 |
DE50111874T DE50111874D1 (de) | 2000-11-30 | 2001-11-30 | Verfahren und vorrichtung zur bestimmung von eigenschaften einer integrierten schaltung |
EP01989545A EP1337838B1 (de) | 2000-11-30 | 2001-11-30 | Verfahren und vorrichtung zur bestimmung von eigenschaften einer integrierten schaltung |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10059516 | 2000-11-30 | ||
DE10059516.2 | 2000-11-30 |
Publications (2)
Publication Number | Publication Date |
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WO2002044699A2 true WO2002044699A2 (de) | 2002-06-06 |
WO2002044699A3 WO2002044699A3 (de) | 2002-09-19 |
Family
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2001/014005 WO2002044699A2 (de) | 2000-11-30 | 2001-11-30 | Verfahren und vorrichtung zur bestimmung von eigenschaften einer integrierten schaltung |
PCT/EP2001/014004 WO2002045014A2 (de) | 2000-11-30 | 2001-11-30 | Verfahren und vorrichtung zur bestimmung von eigenschaften einer integrierten schaltung |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/EP2001/014004 WO2002045014A2 (de) | 2000-11-30 | 2001-11-30 | Verfahren und vorrichtung zur bestimmung von eigenschaften einer integrierten schaltung |
Country Status (7)
Country | Link |
---|---|
US (1) | US7302090B2 (de) |
EP (1) | EP1337838B1 (de) |
JP (1) | JP4216592B2 (de) |
KR (1) | KR100846018B1 (de) |
AU (2) | AU2002227965A1 (de) |
DE (1) | DE50111874D1 (de) |
WO (2) | WO2002044699A2 (de) |
Cited By (4)
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JP2005533292A (ja) * | 2002-07-15 | 2005-11-04 | ケーエルエー・テンコール・テクノロジーズ・コーポレーション | マイクロリソグラフパターンの製作におけるパターンの認定、パターン形成プロセス、又はパターン形成装置 |
EP1745373A2 (de) * | 2004-05-09 | 2007-01-24 | Mentor Graphics Corporation | Defektortidentifikation für die mikroeinrichtungsherstellung und -prüfung |
WO2007147826A1 (en) * | 2006-06-23 | 2007-12-27 | Sagantec Israel Ltd | Layout processing system |
US10216890B2 (en) | 2004-04-21 | 2019-02-26 | Iym Technologies Llc | Integrated circuits having in-situ constraints |
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US7124394B1 (en) | 2003-04-06 | 2006-10-17 | Luminescent Technologies, Inc. | Method for time-evolving rectilinear contours representing photo masks |
US7698665B2 (en) | 2003-04-06 | 2010-04-13 | Luminescent Technologies, Inc. | Systems, masks, and methods for manufacturable masks using a functional representation of polygon pattern |
US7480889B2 (en) * | 2003-04-06 | 2009-01-20 | Luminescent Technologies, Inc. | Optimized photomasks for photolithography |
JP4351928B2 (ja) * | 2004-02-23 | 2009-10-28 | 株式会社東芝 | マスクデータの補正方法、フォトマスクの製造方法及びマスクデータの補正プログラム |
US7251807B2 (en) * | 2005-02-24 | 2007-07-31 | Synopsys, Inc. | Method and apparatus for identifying a manufacturing problem area in a layout using a process-sensitivity model |
US7707541B2 (en) * | 2005-09-13 | 2010-04-27 | Luminescent Technologies, Inc. | Systems, masks, and methods for photolithography |
US7921385B2 (en) | 2005-10-03 | 2011-04-05 | Luminescent Technologies Inc. | Mask-pattern determination using topology types |
US7788627B2 (en) | 2005-10-03 | 2010-08-31 | Luminescent Technologies, Inc. | Lithography verification using guard bands |
WO2007041701A2 (en) | 2005-10-04 | 2007-04-12 | Luminescent Technologies, Inc. | Mask-patterns including intentional breaks |
US7703049B2 (en) | 2005-10-06 | 2010-04-20 | Luminescent Technologies, Inc. | System, masks, and methods for photomasks optimized with approximate and accurate merit functions |
WO2007120279A2 (en) * | 2005-11-18 | 2007-10-25 | Kla-Tencor Technologies Corporation | Methods and systems for utilizing design data in combination with inspection data |
CN101501703B (zh) * | 2006-02-01 | 2012-07-04 | 以色列商·应用材料以色列公司 | 用于评价图案的参数中变化的方法和系统 |
US8331645B2 (en) * | 2006-09-20 | 2012-12-11 | Luminescent Technologies, Inc. | Photo-mask and wafer image reconstruction |
WO2008039674A2 (en) | 2006-09-20 | 2008-04-03 | Luminescent Technologies, Inc. | Photo-mask and wafer image reconstruction |
US8006203B2 (en) * | 2008-08-28 | 2011-08-23 | Synopsys, Inc. | Bulk image modeling for optical proximity correction |
US8797721B2 (en) | 2010-02-02 | 2014-08-05 | Apple Inc. | Portable electronic device housing with outer glass surfaces |
US8463016B2 (en) * | 2010-02-05 | 2013-06-11 | Luminescent Technologies, Inc. | Extending the field of view of a mask-inspection image |
US8612903B2 (en) | 2010-09-14 | 2013-12-17 | Luminescent Technologies, Inc. | Technique for repairing a reflective photo-mask |
US8555214B2 (en) | 2010-09-14 | 2013-10-08 | Luminescent Technologies, Inc. | Technique for analyzing a reflective photo-mask |
US8386968B2 (en) | 2010-11-29 | 2013-02-26 | Luminescent Technologies, Inc. | Virtual photo-mask critical-dimension measurement |
US8458622B2 (en) | 2010-11-29 | 2013-06-04 | Luminescent Technologies, Inc. | Photo-mask acceptance technique |
US9005852B2 (en) | 2012-09-10 | 2015-04-14 | Dino Technology Acquisition Llc | Technique for repairing a reflective photo-mask |
US8653454B2 (en) | 2011-07-13 | 2014-02-18 | Luminescent Technologies, Inc. | Electron-beam image reconstruction |
US9091935B2 (en) | 2013-03-11 | 2015-07-28 | Kla-Tencor Corporation | Multistage extreme ultra-violet mask qualification |
US9494854B2 (en) | 2013-03-14 | 2016-11-15 | Kla-Tencor Corporation | Technique for repairing an EUV photo-mask |
US11798157B2 (en) | 2019-10-11 | 2023-10-24 | The Regents Of The University Of Michigan | Non-destructive imaging techniques for integrated circuits and other applications |
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2001
- 2001-11-30 AU AU2002227965A patent/AU2002227965A1/en not_active Abandoned
- 2001-11-30 US US10/433,250 patent/US7302090B2/en not_active Expired - Lifetime
- 2001-11-30 DE DE50111874T patent/DE50111874D1/de not_active Expired - Lifetime
- 2001-11-30 WO PCT/EP2001/014005 patent/WO2002044699A2/de active IP Right Grant
- 2001-11-30 KR KR1020037007344A patent/KR100846018B1/ko active IP Right Grant
- 2001-11-30 WO PCT/EP2001/014004 patent/WO2002045014A2/de not_active Application Discontinuation
- 2001-11-30 EP EP01989545A patent/EP1337838B1/de not_active Expired - Lifetime
- 2001-11-30 JP JP2002546194A patent/JP4216592B2/ja not_active Expired - Lifetime
- 2001-11-30 AU AU2002238409A patent/AU2002238409A1/en not_active Withdrawn
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US5801954A (en) * | 1996-04-24 | 1998-09-01 | Micron Technology, Inc. | Process for designing and checking a mask layout |
US6081659A (en) * | 1997-05-08 | 2000-06-27 | Lsi Logic Corporation | Comparing aerial image to actual photoresist pattern for masking process characterization |
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US6091845A (en) * | 1998-02-24 | 2000-07-18 | Micron Technology, Inc. | Inspection technique of photomask |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005533292A (ja) * | 2002-07-15 | 2005-11-04 | ケーエルエー・テンコール・テクノロジーズ・コーポレーション | マイクロリソグラフパターンの製作におけるパターンの認定、パターン形成プロセス、又はパターン形成装置 |
US10216890B2 (en) | 2004-04-21 | 2019-02-26 | Iym Technologies Llc | Integrated circuits having in-situ constraints |
US10846454B2 (en) | 2004-04-21 | 2020-11-24 | Iym Technologies Llc | Integrated circuits having in-situ constraints |
US10860773B2 (en) | 2004-04-21 | 2020-12-08 | Iym Technologies Llc | Integrated circuits having in-situ constraints |
EP1745373A2 (de) * | 2004-05-09 | 2007-01-24 | Mentor Graphics Corporation | Defektortidentifikation für die mikroeinrichtungsherstellung und -prüfung |
EP1745373A4 (de) * | 2004-05-09 | 2009-04-15 | Mentor Graphics Corp | Defektortidentifikation für die mikroeinrichtungsherstellung und -prüfung |
WO2007147826A1 (en) * | 2006-06-23 | 2007-12-27 | Sagantec Israel Ltd | Layout processing system |
Also Published As
Publication number | Publication date |
---|---|
JP4216592B2 (ja) | 2009-01-28 |
EP1337838B1 (de) | 2007-01-10 |
EP1337838A2 (de) | 2003-08-27 |
DE50111874D1 (de) | 2007-02-22 |
KR100846018B1 (ko) | 2008-07-11 |
JP2004514938A (ja) | 2004-05-20 |
US7302090B2 (en) | 2007-11-27 |
US20040136587A1 (en) | 2004-07-15 |
WO2002044699A3 (de) | 2002-09-19 |
WO2002045014A2 (de) | 2002-06-06 |
AU2002238409A1 (en) | 2002-06-11 |
AU2002227965A1 (en) | 2002-06-11 |
KR20040022201A (ko) | 2004-03-11 |
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