WO2002043319A8 - Communications architecture for storage-based devices - Google Patents

Communications architecture for storage-based devices

Info

Publication number
WO2002043319A8
WO2002043319A8 PCT/US2001/043474 US0143474W WO0243319A8 WO 2002043319 A8 WO2002043319 A8 WO 2002043319A8 US 0143474 W US0143474 W US 0143474W WO 0243319 A8 WO0243319 A8 WO 0243319A8
Authority
WO
WIPO (PCT)
Prior art keywords
storage
packet
architecture
link architecture
storage link
Prior art date
Application number
PCT/US2001/043474
Other languages
French (fr)
Other versions
WO2002043319A3 (en
WO2002043319A9 (en
WO2002043319A2 (en
Inventor
Yeshik Shin
David D Lee
Deog-Kyoon Jeong
Shing Kong
Dongyun Lee
Original Assignee
Silicon Image
Yeshik Shin
David D Lee
Deog-Kyoon Jeong
Shing Kong
Dongyun Lee
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22957257&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2002043319(A8) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Silicon Image, Yeshik Shin, David D Lee, Deog-Kyoon Jeong, Shing Kong, Dongyun Lee filed Critical Silicon Image
Priority to AU2002236450A priority Critical patent/AU2002236450A1/en
Publication of WO2002043319A2 publication Critical patent/WO2002043319A2/en
Publication of WO2002043319A8 publication Critical patent/WO2002043319A8/en
Publication of WO2002043319A3 publication Critical patent/WO2002043319A3/en
Publication of WO2002043319A9 publication Critical patent/WO2002043319A9/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
    • H04L47/245—Traffic characterised by specific attributes, e.g. priority or QoS using preemption
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/34—Flow control; Congestion control ensuring sequence integrity, e.g. using sequence numbers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/36—Flow control; Congestion control by determining packet size, e.g. maximum transfer unit [MTU]
    • H04L47/365—Dynamic adaptation of the packet size

Abstract

A serial comminications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network such as a storage area network. The Storage link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of comunications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.
PCT/US2001/043474 2000-11-22 2001-11-21 Communications architecture for storage-based devices WO2002043319A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002236450A AU2002236450A1 (en) 2000-11-22 2001-11-21 Communications architecture for storage-based devices

Applications Claiming Priority (28)

Application Number Priority Date Filing Date Title
US25272400P 2000-11-22 2000-11-22
US60/252,724 2000-11-22
US10/045,348 2001-11-07
US10/035,591 2001-11-07
US10/045,625 US7746798B2 (en) 2000-11-22 2001-11-07 Method and system for integrating packet type information with synchronization symbols
US10/045,601 US7340558B2 (en) 2000-11-22 2001-11-07 Multisection memory bank system
US10/036,135 2001-11-07
US10/045,625 2001-11-07
US10/045,297 US7257129B2 (en) 2000-11-22 2001-11-07 Memory architecture with multiple serial communications ports
US10/036,794 US6976201B2 (en) 2000-11-22 2001-11-07 Method and system for host handling of communications errors
US10/045,297 2001-11-07
US10/035,911 US7154905B2 (en) 2000-11-22 2001-11-07 Method and system for nesting of communications packets
US10/036,794 2001-11-07
US10/053,461 2001-11-07
US10/045,393 2001-11-07
US10/053,461 US7113507B2 (en) 2000-11-22 2001-11-07 Method and system for communicating control information via out-of-band symbols
US10/045,348 US20020159450A1 (en) 2000-11-22 2001-11-07 Method and system for asymmetric packet ordering between communications devices
US10/035,911 2001-11-07
US10/037,168 2001-11-07
US10/045,600 US6771192B1 (en) 2000-11-22 2001-11-07 Method and system for DC-balancing at the physical layer
US10/036,135 US20020167945A1 (en) 2000-11-22 2001-11-07 Method and system for packet ordering based on packet type
US10/045,601 2001-11-07
US10/045,606 US20020191603A1 (en) 2000-11-22 2001-11-07 Method and system for dynamic segmentation of communications packets
US10/035,591 US20020154633A1 (en) 2000-11-22 2001-11-07 Communications architecture for storage-based devices
US10/045,600 2001-11-07
US10/037,168 US20020159552A1 (en) 2000-11-22 2001-11-07 Method and system for plesiosynchronous communications with null insertion and removal
US10/045,393 US7039121B2 (en) 2000-11-22 2001-11-07 Method and system for transition-controlled selective block inversion communications
US10/045,606 2001-11-07

Publications (4)

Publication Number Publication Date
WO2002043319A2 WO2002043319A2 (en) 2002-05-30
WO2002043319A8 true WO2002043319A8 (en) 2003-04-17
WO2002043319A3 WO2002043319A3 (en) 2004-02-26
WO2002043319A9 WO2002043319A9 (en) 2004-04-01

Family

ID=22957257

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/043474 WO2002043319A2 (en) 2000-11-22 2001-11-21 Communications architecture for storage-based devices

Country Status (3)

Country Link
US (14) US20020191603A1 (en)
AU (1) AU2002236450A1 (en)
WO (1) WO2002043319A2 (en)

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US6771192B1 (en) 2004-08-03
US20030210162A1 (en) 2003-11-13
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US20020159450A1 (en) 2002-10-31
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