WO2002033825A3 - Method for producing a module, and a module produced using said method - Google Patents

Method for producing a module, and a module produced using said method Download PDF

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Publication number
WO2002033825A3
WO2002033825A3 PCT/DE2001/003976 DE0103976W WO0233825A3 WO 2002033825 A3 WO2002033825 A3 WO 2002033825A3 DE 0103976 W DE0103976 W DE 0103976W WO 0233825 A3 WO0233825 A3 WO 0233825A3
Authority
WO
WIPO (PCT)
Prior art keywords
module
producing
produced
processor
logic unit
Prior art date
Application number
PCT/DE2001/003976
Other languages
German (de)
French (fr)
Other versions
WO2002033825A2 (en
Inventor
Gunnar Schmid
Original Assignee
Siemens Ag
Gunnar Schmid
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Gunnar Schmid filed Critical Siemens Ag
Publication of WO2002033825A2 publication Critical patent/WO2002033825A2/en
Publication of WO2002033825A3 publication Critical patent/WO2002033825A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

The invention relates to a method for producing a module comprising a programmable logic unit (3) whose serial interface (6) is connected to a port (5) of a processor (2). A loading program (8) is loaded into the program memory (7) of the processor (2). Said loading program emulates the transmission protocol of the serial interface (6) and programs the logic unit (3).
PCT/DE2001/003976 2000-10-18 2001-10-18 Method for producing a module, and a module produced using said method WO2002033825A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10051807.9 2000-10-18
DE10051807A DE10051807A1 (en) 2000-10-18 2000-10-18 Method for producing an assembly and assembly produced using the method

Publications (2)

Publication Number Publication Date
WO2002033825A2 WO2002033825A2 (en) 2002-04-25
WO2002033825A3 true WO2002033825A3 (en) 2003-05-22

Family

ID=7660313

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/003976 WO2002033825A2 (en) 2000-10-18 2001-10-18 Method for producing a module, and a module produced using said method

Country Status (2)

Country Link
DE (1) DE10051807A1 (en)
WO (1) WO2002033825A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997049042A1 (en) * 1996-06-21 1997-12-24 Organic Systems, Inc. Dynamically reconfigurable hardware system for real-time control of processes
US6028445A (en) * 1997-12-30 2000-02-22 Xilinx, Inc. Decoder structure and method for FPGA configuration
US6092123A (en) * 1997-07-17 2000-07-18 International Business Machines Corporation Method and apparatus for changing functions of a hardware device using two or more communication channels
US6134707A (en) * 1996-11-14 2000-10-17 Altera Corporation Apparatus and method for in-system programming of integrated circuits containing programmable elements

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997049042A1 (en) * 1996-06-21 1997-12-24 Organic Systems, Inc. Dynamically reconfigurable hardware system for real-time control of processes
US6134707A (en) * 1996-11-14 2000-10-17 Altera Corporation Apparatus and method for in-system programming of integrated circuits containing programmable elements
US6092123A (en) * 1997-07-17 2000-07-18 International Business Machines Corporation Method and apparatus for changing functions of a hardware device using two or more communication channels
US6028445A (en) * 1997-12-30 2000-02-22 Xilinx, Inc. Decoder structure and method for FPGA configuration

Also Published As

Publication number Publication date
WO2002033825A2 (en) 2002-04-25
DE10051807A1 (en) 2002-05-08

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