WO2002033556A2 - Dynamic queuing structure for a memory controller - Google Patents

Dynamic queuing structure for a memory controller Download PDF

Info

Publication number
WO2002033556A2
WO2002033556A2 PCT/US2001/029850 US0129850W WO0233556A2 WO 2002033556 A2 WO2002033556 A2 WO 2002033556A2 US 0129850 W US0129850 W US 0129850W WO 0233556 A2 WO0233556 A2 WO 0233556A2
Authority
WO
WIPO (PCT)
Prior art keywords
memory
queues
service instructions
memory service
instructions
Prior art date
Application number
PCT/US2001/029850
Other languages
French (fr)
Other versions
WO2002033556A3 (en
Inventor
Liuxi Yang
Tung Pham
Original Assignee
Sun Microsystems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems, Inc. filed Critical Sun Microsystems, Inc.
Priority to AU2001293027A priority Critical patent/AU2001293027A1/en
Publication of WO2002033556A2 publication Critical patent/WO2002033556A2/en
Publication of WO2002033556A3 publication Critical patent/WO2002033556A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing

Abstract

A memory management system is disclosed including a processor, a memory control unit coupled to the processor, and a memory coupled to the memory control unit. The memory is configured in a plurality of banks, where the memory control unit includes a dynamic queuing structure, a pointer register defining a plurality of queues associated with the plurality of banks of the memory, an attributes register configured to store attributes of memory service instructions, a content addressable memory configured to store memory access addresses of the memory service instructions, and a queue control configured to control placement of memory service instructions in the plurality of queues based upon the attributes and the memory access address thereof.

Claims

CLAIMS What is claimed is: 1. A memory controller adapted to receive memory service instructions from a processor and adapted to communicate with an external memory organized in a plurality of banks, the memory controller comprising: a plurality of request queues corresponding respectively to the plurality of banks; means for monitoring status of the plurality of queues; means for discriminating characteristics of incoming memory service instructions; and means for allocating the incoming memory service instructions to the plurality of queues based on the status of the queues and the characteristics of the memory service instructions.
2. The memory controller of claim 1, further comprising means for reordering memory service instructions within the plurality of queues.
3. The memory controller of claim 1, further comprising arbiter logic operatively coupled to the plurality of queues and configured to execute the memory service instructions.
4. The memory controller of claim 1, wherein the characteristics comprise type of memory service instruction.
5. The memory controller of claim 1, wherein the characteristics comprise interdependency with other memory service instructions.
20
6. The memory controller of claim 4, wherein the means for allocating places a memory service instruction in a queue depending upon the type of memory service instruction.
7. The memory controller of claim 5, wherein the means for allocating places a memory service instruction in a queue depending upon interdependency with other memory service instructions.
8. The memory controller of claim 1, wherein the means for allocating further comprises means for maintaining a memory service instruction in a float state pending resolution of another operation.
9. A memory management system, comprising: a processor; a memory control unit coupled to the processor; and a memory coupled to the memory control unit, the memory being configured in a plurality of banks; wherein the memory control unit includes a dynamic queuing structure comprising: a pointer register defining a plurality of queues associated with the plurality of banks of the memory; an attributes register configured to store attributes of memory service instructions; a content addressable memory configured to store memory access addresses of the memory service instructions; and
21 a queue control configured to control placement of memory service instructions in the plurality of queues based upon the attributes and the memory access address thereof.
10. The memory management system of claim 9, wherein the memory control unit is integrated with the processor.
11. The memory management system of claim 9, further comprising memory service instruction execution arbiter logic.
12. A method of controlling memory service instructions in a computer system having a processor, a memory configured in a plurality of banks and a memory control unit defining a plurality of queues corresponding to the plurality of banks, the method comprising: monitoring a status of the plurality of queues; discriminating characteristics of an incoming memory service instruction; and placing the incoming memory service instruction in one of the plurality of queues based upon the characteristics thereof and the status of the queues.
13. The method of claim 12, wherein the act of discriminating comprises determining a type of instruction.
14. The method of claim 12, wherein the act of discriminating comprises
22 determining interdependency with other memory service instructions.
15. The method of claim 12, wherein the act of monitoring comprises determining current capacity of the plurality of queues.
16. The method of claim 12, wherein the act of monitoring comprises determining characteristics of memory service instructions in the queues.
17. The method of claim 16, wherein the characteristics include type of memory service instruction.
18. The method of claim 16, wherein the characteristics include interdependency with other memory service instructions.
19. The method of claim 12, wherein the act of placing comprises holding the incoming memory instruction in a float state pending outcome of another operation.
20. The method of claim 12, further comprising optimizing queuing by reordering memory service instructions in the plurality of queues.
23
PCT/US2001/029850 2000-10-19 2001-09-24 Dynamic queuing structure for a memory controller WO2002033556A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001293027A AU2001293027A1 (en) 2000-10-19 2001-09-24 Dynamic queuing structure for a memory controller

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69230400A 2000-10-19 2000-10-19
US09/692,304 2000-10-19

Publications (2)

Publication Number Publication Date
WO2002033556A2 true WO2002033556A2 (en) 2002-04-25
WO2002033556A3 WO2002033556A3 (en) 2003-08-21

Family

ID=24780042

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/029850 WO2002033556A2 (en) 2000-10-19 2001-09-24 Dynamic queuing structure for a memory controller

Country Status (2)

Country Link
AU (1) AU2001293027A1 (en)
WO (1) WO2002033556A2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005109218A1 (en) 2004-04-28 2005-11-17 Intel Corporation Memory controller with command look-ahead
WO2006036798A2 (en) * 2004-09-22 2006-04-06 Qualcomm Incorporated Efficient multi-bank memory queuing system
US20110191527A1 (en) * 2010-01-29 2011-08-04 Kabushiki Kaisha Toshiba Semiconductor storage device and control method thereof
US8285914B1 (en) * 2007-04-16 2012-10-09 Juniper Networks, Inc. Banked memory arbiter for control memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5375215A (en) * 1990-11-09 1994-12-20 Hitachi, Ltd. Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank
US5745913A (en) * 1996-08-05 1998-04-28 Exponential Technology, Inc. Multi-processor DRAM controller that prioritizes row-miss requests to stale banks
US6092158A (en) * 1997-06-13 2000-07-18 Intel Corporation Method and apparatus for arbitrating between command streams

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5375215A (en) * 1990-11-09 1994-12-20 Hitachi, Ltd. Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank
US5745913A (en) * 1996-08-05 1998-04-28 Exponential Technology, Inc. Multi-processor DRAM controller that prioritizes row-miss requests to stale banks
US6092158A (en) * 1997-06-13 2000-07-18 Intel Corporation Method and apparatus for arbitrating between command streams

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005109218A1 (en) 2004-04-28 2005-11-17 Intel Corporation Memory controller with command look-ahead
US7418540B2 (en) 2004-04-28 2008-08-26 Intel Corporation Memory controller with command queue look-ahead
WO2006036798A2 (en) * 2004-09-22 2006-04-06 Qualcomm Incorporated Efficient multi-bank memory queuing system
WO2006036798A3 (en) * 2004-09-22 2007-02-01 Qualcomm Inc Efficient multi-bank memory queuing system
US8285914B1 (en) * 2007-04-16 2012-10-09 Juniper Networks, Inc. Banked memory arbiter for control memory
US20110191527A1 (en) * 2010-01-29 2011-08-04 Kabushiki Kaisha Toshiba Semiconductor storage device and control method thereof

Also Published As

Publication number Publication date
AU2001293027A1 (en) 2002-04-29
WO2002033556A3 (en) 2003-08-21

Similar Documents

Publication Publication Date Title
US6401155B1 (en) Interrupt/software-controlled thread processing
US8516163B2 (en) Hardware-based concurrent direct memory access (DMA) engines on serial rapid input/output SRIO interface
CN101609438B (en) Memory system, access control method therefor, and computer program
US6438557B1 (en) System and method for performing context switching and rescheduling of a processor
US6292871B1 (en) Loading accessed data from a prefetch buffer to a least recently used position in a cache
EP2912559B1 (en) Communication of message signalled interrupts
KR20070086640A (en) Priority scheme for executing commands in memories
WO2003073300A1 (en) Method and apparatus to control memory accesses
US8356143B1 (en) Prefetch mechanism for bus master memory access
US20040148606A1 (en) Multi-thread computer
WO2001038970A2 (en) Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks
US8032658B2 (en) Computer architecture and process for implementing a virtual vertical perimeter framework for an overloaded CPU having multiple network interfaces
JP5340658B2 (en) Command-optimized memory controller read queue dynamic optimization
CN114610472A (en) Multi-process management method in heterogeneous computing and computing equipment
WO2002033556A2 (en) Dynamic queuing structure for a memory controller
US6976110B2 (en) Method and apparatus for reducing interrupt latency by dynamic buffer sizing
US6745296B2 (en) System and method for providing cacheable smram
US8533368B2 (en) Buffering device and buffering method
US6282144B1 (en) Multi-ported memory with asynchronous and synchronous protocol
JP2001290704A (en) Device and method for controlling multiprocess
JP2002041358A (en) Processor system
EP4160423B1 (en) Memory device, memory device operating method, and electronic device including memory device
KR100284784B1 (en) Memory data processing system and method and communication system having system
JPH05241958A (en) Virtual storage control system
JPH09237224A (en) Disk array device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase in:

Ref country code: JP