WO2002031869A3 - Method and apparatus for processing thin metal layers - Google Patents

Method and apparatus for processing thin metal layers Download PDF

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Publication number
WO2002031869A3
WO2002031869A3 PCT/US2001/031391 US0131391W WO0231869A3 WO 2002031869 A3 WO2002031869 A3 WO 2002031869A3 US 0131391 W US0131391 W US 0131391W WO 0231869 A3 WO0231869 A3 WO 0231869A3
Authority
WO
WIPO (PCT)
Prior art keywords
metal layer
regions
melted
region
irradiation
Prior art date
Application number
PCT/US2001/031391
Other languages
French (fr)
Other versions
WO2002031869A9 (en
WO2002031869A2 (en
Inventor
James S Im
Original Assignee
Univ Columbia
James S Im
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Columbia, James S Im filed Critical Univ Columbia
Priority to EP01979560A priority Critical patent/EP1259985A2/en
Priority to CA002389607A priority patent/CA2389607A1/en
Priority to AU2002211507A priority patent/AU2002211507A1/en
Priority to US10/129,159 priority patent/US7115503B2/en
Priority to MXPA02005590A priority patent/MXPA02005590A/en
Priority to JP2002535162A priority patent/JP4599032B2/en
Publication of WO2002031869A2 publication Critical patent/WO2002031869A2/en
Publication of WO2002031869A3 publication Critical patent/WO2002031869A3/en
Publication of WO2002031869A9 publication Critical patent/WO2002031869A9/en
Priority to US11/502,056 priority patent/US7709378B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/94—Laser ablative material removal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/955—Melt-back

Abstract

A method and apparatus for processing a thin metal layer on a substrate to control the grain size, grain shape, and grain boundary location and orientation in the metal layer by irradiating the metal layer with a first excimer laser pulse having an intensity pattern defined by a mask to have shadow regions and beamlets. Each region of the metal layer overlapped by a beamlet is melted throughout its entire thickness, and each region of the metal layer overlapped by a shadow region remains at least partially unmelted. Each at least partially unmelted region adjoins adjacent melted regions. After irradiation by the first excimer laser pulse, the melted regions of the metal layer are permitted to resolidify. During resolidification, the at least partially unmelted regions seed growth of grains in adjoining melted regions to produce larger grains. After completion of resolidification of the melted regions following irradiation by the first excimer laser pulse, the metal layer is irradiated by a second excimer laser pulse having a shifted intensity pattern so that the shadow regions overlap regions of the metal layer having fewer and larger grains. Each region of the metal layer overlapped by one of the shifted beamlets is melted throughout its entire thickness, while each region of the metal layer overlapped by one of the shifted shadow regions remains at least partially unmelted. During resolidification of the melted regions after irradiation by the second radiation beam pulse, the larger grains in the at least partially unmelted regions seed growth of even larger grains in adjoining melted regions. The irradiation, resolidification and re-irradiation of the metal layer may be repeated, as needed, until a desired grain structure is obtained in the metal layer.
PCT/US2001/031391 2000-10-10 2001-10-09 Method and apparatus for processing thin metal layers WO2002031869A2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
EP01979560A EP1259985A2 (en) 2000-10-10 2001-10-09 Method and apparatus for processing thin metal layers
CA002389607A CA2389607A1 (en) 2000-10-10 2001-10-09 Method and apparatus for processing thin metal layers
AU2002211507A AU2002211507A1 (en) 2000-10-10 2001-10-09 Method and apparatus for processing thin metal layers
US10/129,159 US7115503B2 (en) 2000-10-10 2001-10-09 Method and apparatus for processing thin metal layers
MXPA02005590A MXPA02005590A (en) 2000-10-10 2001-10-09 Method and apparatus for processing thin metal layers.
JP2002535162A JP4599032B2 (en) 2000-10-10 2001-10-09 Method and apparatus for processing thin metal layers
US11/502,056 US7709378B2 (en) 2000-10-10 2006-08-10 Method and apparatus for processing thin metal layers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US23919400P 2000-10-10 2000-10-10
US60/239,194 2000-10-10

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US10129159 A-371-Of-International 2001-10-09
US11/502,056 Continuation US7709378B2 (en) 2000-10-10 2006-08-10 Method and apparatus for processing thin metal layers

Publications (3)

Publication Number Publication Date
WO2002031869A2 WO2002031869A2 (en) 2002-04-18
WO2002031869A3 true WO2002031869A3 (en) 2002-09-19
WO2002031869A9 WO2002031869A9 (en) 2004-04-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/031391 WO2002031869A2 (en) 2000-10-10 2001-10-09 Method and apparatus for processing thin metal layers

Country Status (10)

Country Link
US (2) US7115503B2 (en)
EP (1) EP1259985A2 (en)
JP (1) JP4599032B2 (en)
KR (1) KR100854834B1 (en)
CN (1) CN1404627A (en)
AU (1) AU2002211507A1 (en)
CA (1) CA2389607A1 (en)
MX (1) MXPA02005590A (en)
TW (1) TW521387B (en)
WO (1) WO2002031869A2 (en)

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