WO2002029968A3 - Quardrature direct-conversion demodolator using dc offset compensation - Google Patents

Quardrature direct-conversion demodolator using dc offset compensation Download PDF

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Publication number
WO2002029968A3
WO2002029968A3 PCT/US2001/042439 US0142439W WO0229968A3 WO 2002029968 A3 WO2002029968 A3 WO 2002029968A3 US 0142439 W US0142439 W US 0142439W WO 0229968 A3 WO0229968 A3 WO 0229968A3
Authority
WO
WIPO (PCT)
Prior art keywords
input signal
control logic
signal
baseband
gain
Prior art date
Application number
PCT/US2001/042439
Other languages
French (fr)
Other versions
WO2002029968A2 (en
Inventor
Keith R Baldwin
Patrick J Landy
Mark A Webster
R Douglas Schultz
John S Prentice
Original Assignee
Intersil Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intersil Inc filed Critical Intersil Inc
Priority to DE10196720T priority Critical patent/DE10196720T1/en
Priority to JP2002533468A priority patent/JP2004511157A/en
Priority to AU2002213434A priority patent/AU2002213434A1/en
Publication of WO2002029968A2 publication Critical patent/WO2002029968A2/en
Publication of WO2002029968A3 publication Critical patent/WO2002029968A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/30—Circuits for homodyne or synchrodyne receivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
    • H03D3/008—Compensating DC offsets

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

A wireless communication device (200) including a radio frequency (RF) circuit, a ZIF tranceiver (201) and a baseband processor (203). The ZIF transceiver (201) includes an RF mixer circuit (301) that converts the RF signal to a baseband input signal, a summing junction (303) that substracts a DC offset from the baseband input signal to provide an adjusted baseband input signal, and a baseband amplifier (307) that receives the adjusted baseband input signal and that asserts an amplified input signal based on a gain adjust signal. The baseband processor (203) includes gain control logic (345), DC control logic (347) and a gain interface (331). The gain control logic receives the amplified input signal, estimates input signal power and asserts the gain adjust signal in an attempt to keep the input signal power at a target power level. The DC control logic estimates an amount of DC in the amplified input signal and provided the DC offset in an attempt to reduce DC in the amplified input signal. The gain interface converts gain levels between the gain control logic and the DC control logic. The RF signal may include in-phase (I) and quadrature (Q) portions, where the RF mixer circuit splits I and Q baseband input signals from the RF signal. Operation is substantially identical for both I an Q channels. The DC control logic operates to remove or otherwise eliminate DC from the received signal that is provided to decoders in the baseband processor.
PCT/US2001/042439 2000-10-02 2001-10-01 Quardrature direct-conversion demodolator using dc offset compensation WO2002029968A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE10196720T DE10196720T1 (en) 2000-10-02 2001-10-01 DC compensation system for a wireless communication device arranged in a zero intermediate frequency architecture
JP2002533468A JP2004511157A (en) 2000-10-02 2001-10-01 DC compensator for wireless communication devices set to zero intermediate frequency architecture
AU2002213434A AU2002213434A1 (en) 2000-10-02 2001-10-01 A dc compensation system for a wireless communication device configured in a zero intermediate frequency architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/678,901 US6560448B1 (en) 2000-10-02 2000-10-02 DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture
US09/678,901 2000-10-02

Publications (2)

Publication Number Publication Date
WO2002029968A2 WO2002029968A2 (en) 2002-04-11
WO2002029968A3 true WO2002029968A3 (en) 2002-06-13

Family

ID=24724761

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/042439 WO2002029968A2 (en) 2000-10-02 2001-10-01 Quardrature direct-conversion demodolator using dc offset compensation

Country Status (7)

Country Link
US (1) US6560448B1 (en)
JP (1) JP2004511157A (en)
CN (1) CN1531774A (en)
AU (1) AU2002213434A1 (en)
DE (1) DE10196720T1 (en)
TW (1) TW522693B (en)
WO (1) WO2002029968A2 (en)

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Also Published As

Publication number Publication date
AU2002213434A1 (en) 2002-04-15
TW522693B (en) 2003-03-01
WO2002029968A2 (en) 2002-04-11
US6560448B1 (en) 2003-05-06
JP2004511157A (en) 2004-04-08
CN1531774A (en) 2004-09-22
DE10196720T1 (en) 2003-11-13

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