WO2002025454A2 - Memory module having buffer for isolating stacked memory devices - Google Patents

Memory module having buffer for isolating stacked memory devices Download PDF

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Publication number
WO2002025454A2
WO2002025454A2 PCT/US2001/028627 US0128627W WO0225454A2 WO 2002025454 A2 WO2002025454 A2 WO 2002025454A2 US 0128627 W US0128627 W US 0128627W WO 0225454 A2 WO0225454 A2 WO 0225454A2
Authority
WO
WIPO (PCT)
Prior art keywords
memory
buffer
bus
module
coupled
Prior art date
Application number
PCT/US2001/028627
Other languages
French (fr)
Other versions
WO2002025454A3 (en
Inventor
John Halbert
Randy M. Bonella
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/666,528 external-priority patent/US6487102B1/en
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to AU2001289067A priority Critical patent/AU2001289067A1/en
Priority to KR1020037003689A priority patent/KR100554081B1/en
Priority to EP01968854A priority patent/EP1320804A2/en
Publication of WO2002025454A2 publication Critical patent/WO2002025454A2/en
Publication of WO2002025454A3 publication Critical patent/WO2002025454A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports

Definitions

  • Fig. 1 is a block diagram of a prior art memory system.
  • the system of Fig. 1 includes three memory modules 10, 12, and 14 that are coupled to a memory controller 16 through a bus 18.
  • Each memory module is fabricated on a circuit board that plugs into a connector 20 on a mother board 22.
  • Each module includes multiple memory devices 24, 26, and 28 that are coupled to the bus 18 to allow the memory controller to access the memory devices .
  • each data line in the bus 18 has a total capacitance that equals the sum of the capacitance of each portion of the signal line running through sections A, B, and C of the bus, plus the capacitance of the portion of the data line in sections 30, 32, and 34 that couple the memory devices to the bus, plus the sum of the input capacitance of all of the memory devices (which are attached to sections 30, 32, and 34 in parallel).
  • FIG. 1 is a block diagram of a prior art memory system.
  • Fig. 2 is a block diagram of an embodiment of a memory module in accordance " with the present invention.
  • Fig. 3 is a side view showing the mechanical arrangement of an embodiment of a memory module in accordance with the present invention.
  • Fig. 4 is a block diagram of an embodiment of a memory system in accordance with the present invention.
  • FIG. 2 is a block diagram of an embodiment of a memory module 100 in accordance with the present invention.
  • Module 100 includes a first memory device 104 which is mounted on a circuit board 108.
  • a second memory device 106 is stacked on top of the first memory device to form a stack 102.
  • a buffer 110 is mounted on the circuit board and electrically coupled to the memory devices 104 and 106 through signal lines 112.
  • a connector 114 is attached to the circuit board for coupling the memory module to a bus that leads to a memory controller on another circuit board, e.g., a computer mother board.
  • the buffer 110 is arranged to capacitively isolate the stack of memory devices from the bus. Therefore, the capacitive loading seen by a memory controller (or other device) driving the bus is reduced. This increases the maximum operating speed of the memory module and reduces power consumption.
  • the buffer 110 sends and receives signals to and from the memory controller through connector 114 over signal lines 120.
  • the buffer 110 is designed to receive signals from the memory controller over a first bus and redrive them back out the connector over signal lines 122 (shown in broken lines) and to a second memory module over a second bus.
  • Fig. 3 is a side view showing the mechanical arrangement of an embodiment of a memory module in accordance with the present invention.
  • the stack 102 can be extended to include additional memory devices (shown in broken lines). Additional stacks can also be added, and they can be buffered by the first buffer 110, or a separate buffer can be used for each stack.
  • Fig. 4 is a block diagram of an embodiment of a memory system in accordance with the present invention.
  • the system of Fig. 4 includes two modules 100A and 100B coupled to a memory controller 116 on a computer mother board 117 through a bus system 118 which includes buses 118 A and 118B.
  • the modules may be coupled through connectors 130A and 130B which plug into connectors 132A and 132B, respectively, on the mother board.
  • Each module a stack of memory devices 102A,102B and a buffer 110A, 110B that isolates the corresponding stack from the bus system.
  • the modules are coupled to the memory controller in a point-to-point arrangement.
  • the memory controller 116 is coupled to module 100A, which is designed to receive signals from the memory controller and redrive them to module 100B.
  • module 100A which is designed to receive signals from the memory controller and redrive them to module 100B.
  • the use of point-to-point wiring further reduces the capacitive loading seen by the memory controller.
  • the modules 110A and HOB and memory controller 116 may be coupled together in a multi-drop arrangement in which both of the modules are essentially coupled in parallel on a single bus.
  • the memory controller 116 is shown in Fig. 4 as part of a central processing unit (CPU) 126, however, it may alternatively be implemented as one chip of a chipset, or in any other suitable form.
  • the memory system shown in Fig. 4 includes two memory modules for purposes of illustration, but may be implemented with only a single memory module or with any number of modules.
  • the buffers need not be mounted on the memory modules, but can also be mounted on the mother board or any other device on which the bus system resides.
  • the stacks of memory devices need not be mounted on modules. Instead, an entire memory system in accordance with the present invention may be fabricated on a single circuit board including the memory controller, bus, stacks of memory devices, and buffers arranged to capacitively isolate the stacks from the bus.

Abstract

The present invention utilizes a buffer to isolate a stack of memory devices, thereby taking advantage of the increased memory density available from stacked memory devices while reducing capacitive loading. A memory module in accordance with the present invention may include a stack of memory devices and a buffer coupled to the first and second memory devices and arranged to capacitively isolate the first and second memory devices from a bus. In a memory system in accordance with the present invention, multiple buffered stacks of memory devices are preferably coupled in a point-to-point arrangement, thereby further reducing capacitive loading.

Description

MEMORY MODULE HAVING BUFFER FOR ISOLATING STACKED MEMORY
DEVICES
BACKGROUND OF THE INVENTION Fig. 1 is a block diagram of a prior art memory system. The system of Fig. 1 includes three memory modules 10, 12, and 14 that are coupled to a memory controller 16 through a bus 18. Each memory module is fabricated on a circuit board that plugs into a connector 20 on a mother board 22. Each module includes multiple memory devices 24, 26, and 28 that are coupled to the bus 18 to allow the memory controller to access the memory devices .
To increase the memory density of the modules, memory devices can be stacked on top of each other, thereby increasing the memory capacity of each module without increasing the space required on the circuit board. Stacking memory devices, however, increases the capacitive loading of the signals on the bus. For example, from the perspective of the memory controller 16, each data line in the bus 18 has a total capacitance that equals the sum of the capacitance of each portion of the signal line running through sections A, B, and C of the bus, plus the capacitance of the portion of the data line in sections 30, 32, and 34 that couple the memory devices to the bus, plus the sum of the input capacitance of all of the memory devices (which are attached to sections 30, 32, and 34 in parallel). If additional memory devices are stacked on devices 24, 26, and 28, then the capacitance of the additional devices are added to the total capacitance seen by the controller. Therefore, when the memory controller drives a data signal onto the bus, it must overcome the combined capacitance of all of the stacked memory devices. This heavy capacitive loading reduces the maximum operating speed and increases the power consumption by the memory system, especially at higher operating frequencies.
BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a prior art memory system. Fig. 2 is a block diagram of an embodiment of a memory module in accordance " with the present invention.
Fig. 3 is a side view showing the mechanical arrangement of an embodiment of a memory module in accordance with the present invention. Fig. 4 is a block diagram of an embodiment of a memory system in accordance with the present invention.
DETAILED DESCRIPTION Fig. 2 is a block diagram of an embodiment of a memory module 100 in accordance with the present invention. Module 100 includes a first memory device 104 which is mounted on a circuit board 108. A second memory device 106 is stacked on top of the first memory device to form a stack 102. A buffer 110 is mounted on the circuit board and electrically coupled to the memory devices 104 and 106 through signal lines 112. A connector 114 is attached to the circuit board for coupling the memory module to a bus that leads to a memory controller on another circuit board, e.g., a computer mother board. The buffer 110 is arranged to capacitively isolate the stack of memory devices from the bus. Therefore, the capacitive loading seen by a memory controller (or other device) driving the bus is reduced. This increases the maximum operating speed of the memory module and reduces power consumption.
The buffer 110 sends and receives signals to and from the memory controller through connector 114 over signal lines 120. In a preferred embodiment, the buffer 110 is designed to receive signals from the memory controller over a first bus and redrive them back out the connector over signal lines 122 (shown in broken lines) and to a second memory module over a second bus.
Fig. 3 is a side view showing the mechanical arrangement of an embodiment of a memory module in accordance with the present invention. The stack 102 can be extended to include additional memory devices (shown in broken lines). Additional stacks can also be added, and they can be buffered by the first buffer 110, or a separate buffer can be used for each stack.
Fig. 4 is a block diagram of an embodiment of a memory system in accordance with the present invention. The system of Fig. 4 includes two modules 100A and 100B coupled to a memory controller 116 on a computer mother board 117 through a bus system 118 which includes buses 118 A and 118B. The modules may be coupled through connectors 130A and 130B which plug into connectors 132A and 132B, respectively, on the mother board. Each module a stack of memory devices 102A,102B and a buffer 110A, 110B that isolates the corresponding stack from the bus system. In the example of Fig. 4, the modules are coupled to the memory controller in a point-to-point arrangement. That is, the memory controller 116 is coupled to module 100A, which is designed to receive signals from the memory controller and redrive them to module 100B. The use of point-to-point wiring further reduces the capacitive loading seen by the memory controller. Alternatively, the modules 110A and HOB and memory controller 116 may be coupled together in a multi-drop arrangement in which both of the modules are essentially coupled in parallel on a single bus.
The memory controller 116 is shown in Fig. 4 as part of a central processing unit (CPU) 126, however, it may alternatively be implemented as one chip of a chipset, or in any other suitable form. The memory system shown in Fig. 4 includes two memory modules for purposes of illustration, but may be implemented with only a single memory module or with any number of modules. The buffers need not be mounted on the memory modules, but can also be mounted on the mother board or any other device on which the bus system resides. Moreover, the stacks of memory devices need not be mounted on modules. Instead, an entire memory system in accordance with the present invention may be fabricated on a single circuit board including the memory controller, bus, stacks of memory devices, and buffers arranged to capacitively isolate the stacks from the bus. The advantages of the present invention can be realized wherever memory devices are stacked by buffering the stack from other components, thereby reducing the capacitance load seen by the other component.
Having described and illustrated the principles of the invention in some preferred embodiments thereof, it should be apparent that the invention can be modified in arrangement and detail without departing from such principles. We claim all modifications and variations coming within the spirit and scope of the following claims.

Claims

1. A memory system comprising: a first memory device; a second memory device stacked on the first memory device; and a buffer coupled to the first and second memory devices.
2. A memory system according to claim 1 further comprising a third memory device stacked on the second memory device and coupled to the buffer.
3. A memory system according to claim 1 further comprising a bus coupled to the buffer.
4. A memory system according to claim 3 further comprising a memory controller coupled to the bus.
5. A memory system according to claim 1 wherein the buffer is a first buffer and further comprising: a third memory device; ; a fourth memory device stacked on the third memory device; and a second buffer coupled to the third and fourth memory devices and to the first buffer.
6. A memory system according to claim 5 wherein the first buffer is adapted to receive a signal and redrive the signal to the second buffer.
7. A memory system according to claim 5 wherein the first buffer is adapted to receive a plurality of signals and redrive the plurality of signals to the second buffer.
8. A memory system according to claim 5 further comprising a memory controller coupled to the first buffer.
9. A memory system according to claim 8 wherein the memory controller, the first buffer, and the second buffer are coupled together in a multi-drop arrangement.
10. A memory system according to claim 8 wherein the memory controller, the first buffer, and the second buffer are coupled together in a point-to-point arrangement.
11. A memory module comprising: a first memory device; a second memory device stacked on the first memory device; and a buffer coupled to the first and second memory devices and arranged to capacitively isolate the first and second memory devices from a bus.
12. A memory module according to claim 11 further comprising a connector attached to the module and adapted to couple the module to a bus.
13. A memory module according to claim 11 further comprising a third memory device stacked on the second memory device and coupled to the buffer.
14. A memory module according to claim 11 wherein the memory module is adapted to receive a signal from the bus and to redrive the signal to another memory module.
15. A memory module according to claim 11 wherein the memory module is adapted to receive a plurality of signals from the bus and to redrive the plurality of signals to another memory module.
16. A memory module according to claim 11 wherein the buffer is adapted to receive a signal from the bus and to redrive the signal to another memory module.
17. A memory system comprising: a bus; a stack of memory devices; and a buffer coupled between the stack of memory devices and the memory bus.
18. A memory system according to claim 17 further comprising: a second stack of memory devices; and a second buffer coupled between the second stack of memory devices and the bus.
19. A memory system according to claim 17 wherein the buffer is a first buffer and further comprising: a second stack of memory devices; and a second buffer coupled between the second stack of memory devices and the first buffer.
20. A memory system according to claim 17 further including a memory controller coupled to the bus.
21. A memory system according to claim 17 wherein the stack of memory devices is mounted on a memory module.
22. A memory system according to claim 21 wherein the buffer is mounted on the memory module.
23. A memory system according to claim 21 wherein the bus is fabricated on a circuit board and the buffer is mounted on the circuit board.
PCT/US2001/028627 2000-09-14 2001-09-14 Memory module having buffer for isolating stacked memory devices WO2002025454A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2001289067A AU2001289067A1 (en) 2000-09-14 2001-09-14 Memory module having buffer for isolating stacked memory devices
KR1020037003689A KR100554081B1 (en) 2000-09-14 2001-09-14 Memory Module having Buffer for Isolating Stacked Memory Devices
EP01968854A EP1320804A2 (en) 2000-09-14 2001-09-14 Memory module having buffer for isolating stacked memory devices

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US23259600P 2000-09-14 2000-09-14
US60/232,596 2000-09-14
US09/666,528 US6487102B1 (en) 2000-09-18 2000-09-18 Memory module having buffer for isolating stacked memory devices
US09/666,528 2000-09-18

Publications (2)

Publication Number Publication Date
WO2002025454A2 true WO2002025454A2 (en) 2002-03-28
WO2002025454A3 WO2002025454A3 (en) 2002-08-22

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EP (1) EP1320804A2 (en)
KR (1) KR100554081B1 (en)
CN (1) CN1484833A (en)
AU (1) AU2001289067A1 (en)
TW (1) TW528948B (en)
WO (1) WO2002025454A2 (en)

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US7461188B2 (en) * 2000-08-11 2008-12-02 Micron Technology, Inc. Capacitive multidrop bus compensation
US7685364B2 (en) 2005-09-26 2010-03-23 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US7729151B2 (en) 2005-09-26 2010-06-01 Rambus Inc. System including a buffered memory module
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack

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US20050289316A1 (en) * 2004-06-24 2005-12-29 David Durham Mechanism for sequestering memory for a bus device
US7577760B2 (en) 2005-05-10 2009-08-18 Samsung Electronics Co., Ltd. Memory systems, modules, controllers and methods using dedicated data and control busses
KR100763352B1 (en) * 2005-05-10 2007-10-04 삼성전자주식회사 Memory systems, modules, controllers and methods using dedicated data and control busses
US8516185B2 (en) * 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US8582373B2 (en) * 2010-08-31 2013-11-12 Micron Technology, Inc. Buffer die in stacks of memory dies and methods
KR20180004562A (en) * 2016-07-04 2018-01-12 에스프린팅솔루션 주식회사 Electronic apparatus

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US9865329B2 (en) 2005-09-26 2018-01-09 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US10381067B2 (en) 2005-09-26 2019-08-13 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US10535398B2 (en) 2005-09-26 2020-01-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US10672458B1 (en) 2005-09-26 2020-06-02 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US11043258B2 (en) 2005-09-26 2021-06-22 Rambus Inc. Memory system topologies including a memory die stack
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
US11727982B2 (en) 2005-09-26 2023-08-15 Rambus Inc. Memory system topologies including a memory die stack

Also Published As

Publication number Publication date
TW528948B (en) 2003-04-21
KR20030048036A (en) 2003-06-18
CN1484833A (en) 2004-03-24
EP1320804A2 (en) 2003-06-25
AU2001289067A1 (en) 2002-04-02
WO2002025454A3 (en) 2002-08-22
KR100554081B1 (en) 2006-02-22

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