WO2002025449A3 - Integrated circuit having a programmable address in an i2c environment - Google Patents

Integrated circuit having a programmable address in an i2c environment Download PDF

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Publication number
WO2002025449A3
WO2002025449A3 PCT/US2001/028585 US0128585W WO0225449A3 WO 2002025449 A3 WO2002025449 A3 WO 2002025449A3 US 0128585 W US0128585 W US 0128585W WO 0225449 A3 WO0225449 A3 WO 0225449A3
Authority
WO
WIPO (PCT)
Prior art keywords
modification
address
programming
environment
integrated circuit
Prior art date
Application number
PCT/US2001/028585
Other languages
French (fr)
Other versions
WO2002025449A2 (en
Inventor
David Lawrence Albean
Original Assignee
Thomson Licensing Sa
David Lawrence Albean
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing Sa, David Lawrence Albean filed Critical Thomson Licensing Sa
Priority to AU2001289054A priority Critical patent/AU2001289054A1/en
Priority to MXPA03002282A priority patent/MXPA03002282A/en
Priority to JP2002529383A priority patent/JP2004510228A/en
Priority to EP01968840A priority patent/EP1323048A2/en
Priority to KR10-2003-7003778A priority patent/KR20030033063A/en
Publication of WO2002025449A2 publication Critical patent/WO2002025449A2/en
Publication of WO2002025449A3 publication Critical patent/WO2002025449A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0052—Assignment of addresses or identifiers to the modules of a bus system

Abstract

An apparatus, system and method provides for the modification or programmability of an address of an I2C device. The modification or programming may be accompmlished via an input signal received by an I/O terminal of the device. In another form, the present invention also provides for substantially simultaneous modification of first and second addresses of respective first and second I2C devices. The modification or programming may be accomplished via an input signal received by an I/O terminal coupled to both the first and second I2C devices. The present invention obviates bus contention problems in an I¿2?C bus/protocol system due to IC address conflict through the ability to modify (change) or program the I?2¿C address. Modification or programming can be accommplished during the design phase or thereafter via software.
PCT/US2001/028585 2000-09-19 2001-09-13 Integrated circuit having a programmable address in an i2c environment WO2002025449A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AU2001289054A AU2001289054A1 (en) 2000-09-19 2001-09-13 Integrated circuit having a programmable address in an i2c environment
MXPA03002282A MXPA03002282A (en) 2000-09-19 2001-09-13 Integrated circuit having a programmable address in an i2.
JP2002529383A JP2004510228A (en) 2000-09-19 2001-09-13 Integrated circuit with programmable address in I2C environment
EP01968840A EP1323048A2 (en) 2000-09-19 2001-09-13 Integrated circuit having a programmable address in a i2c environment
KR10-2003-7003778A KR20030033063A (en) 2000-09-19 2001-09-13 Integrated circuit having a programmable address in an i2c environment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US66469700A 2000-09-19 2000-09-19
US09/664,697 2000-09-19

Publications (2)

Publication Number Publication Date
WO2002025449A2 WO2002025449A2 (en) 2002-03-28
WO2002025449A3 true WO2002025449A3 (en) 2003-02-20

Family

ID=24667065

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/028585 WO2002025449A2 (en) 2000-09-19 2001-09-13 Integrated circuit having a programmable address in an i2c environment

Country Status (7)

Country Link
EP (1) EP1323048A2 (en)
JP (1) JP2004510228A (en)
KR (1) KR20030033063A (en)
CN (1) CN1461440A (en)
AU (1) AU2001289054A1 (en)
MX (1) MXPA03002282A (en)
WO (1) WO2002025449A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050086396A1 (en) * 2001-12-28 2005-04-21 Francois Bernard Communication system
WO2005106689A1 (en) * 2004-04-29 2005-11-10 Koninklijke Philips Electronics N.V. Bus system for selectively controlling a plurality of identical slave circuits connected to the bus and method therefore
JP4679310B2 (en) * 2005-09-06 2011-04-27 株式会社リコー Image forming apparatus
JP5314563B2 (en) * 2009-10-22 2013-10-16 旭化成エレクトロニクス株式会社 Inter-device communication system and communication device
US9710422B2 (en) 2014-12-15 2017-07-18 Intel Corporation Low cost low overhead serial interface for power management and other ICs
JP6254517B2 (en) * 2014-12-22 2017-12-27 富士通フロンテック株式会社 Media handling device
US10268614B2 (en) 2016-04-19 2019-04-23 Nokia Of America Corporation Method and apparatus for a segmented on-chip digital interface block
CN108681517B (en) * 2018-05-09 2020-09-01 广州计量检测技术研究院 Method and system for converting I2C device address
FR3097987A1 (en) * 2019-06-26 2021-01-01 STMicroelectronics (Alps) SAS METHOD OF ADDRESSING AN INTEGRATED CIRCUIT ON A BUS AND CORRESPONDING DEVICE

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5636342A (en) * 1995-02-17 1997-06-03 Dell Usa, L.P. Systems and method for assigning unique addresses to agents on a system management bus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5636342A (en) * 1995-02-17 1997-06-03 Dell Usa, L.P. Systems and method for assigning unique addresses to agents on a system management bus

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"ST24C04, ST25C04, ST24W04, ST25W04, 4kBit Serial I2C Bus EEPROM with user defined Block Write Protection", ANNOUNCEMENT ST MICROELECTRONICS, XX, XX, PAGE(S) 1-16, XP002206612 *
ANONYMOUS: "Identical I2C Components Sharing a Unique I2C Address", RESEARCH DISCLOSURE, KENNETH MASON PUBLICATIONS, HAMPSHIRE, GB, vol. 41, no. 413, 1 September 1998 (1998-09-01), XP002212259, ISSN: 0374-4353 *

Also Published As

Publication number Publication date
MXPA03002282A (en) 2003-06-24
CN1461440A (en) 2003-12-10
AU2001289054A1 (en) 2002-04-02
EP1323048A2 (en) 2003-07-02
KR20030033063A (en) 2003-04-26
WO2002025449A2 (en) 2002-03-28
JP2004510228A (en) 2004-04-02

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