WO2002023601A3 - Method for contact etching using a hardmask and advanced resist technology - Google Patents

Method for contact etching using a hardmask and advanced resist technology Download PDF

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Publication number
WO2002023601A3
WO2002023601A3 PCT/US2001/026647 US0126647W WO0223601A3 WO 2002023601 A3 WO2002023601 A3 WO 2002023601A3 US 0126647 W US0126647 W US 0126647W WO 0223601 A3 WO0223601 A3 WO 0223601A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
hardmask
hard mask
forming
contact etching
Prior art date
Application number
PCT/US2001/026647
Other languages
French (fr)
Other versions
WO2002023601A2 (en
Inventor
Michael Stetter
Uwe Paul Schroeder
Original Assignee
Infineon Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp filed Critical Infineon Technologies Corp
Publication of WO2002023601A2 publication Critical patent/WO2002023601A2/en
Publication of WO2002023601A3 publication Critical patent/WO2002023601A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

A method for forming contact holes, in accordance with the present invention, includes forming a hard mask layer on a dielectric layer, forming an anti-reflection coating of less than or equal to 1000 angstroms in thickness on the hard mask layer, and forming a silicon containing imaging resist layer on the anti-reflection layer. The imaging resist layer is patterned and the anti-reflection coating and the hard mask are etched by employing the imaging resist layer as a mask. The dielectric layer is then etched by employing the hard mask as a mask.
PCT/US2001/026647 2000-09-14 2001-08-27 Method for contact etching using a hardmask and advanced resist technology WO2002023601A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US66221400A 2000-09-14 2000-09-14
US09/662,214 2000-09-14

Publications (2)

Publication Number Publication Date
WO2002023601A2 WO2002023601A2 (en) 2002-03-21
WO2002023601A3 true WO2002023601A3 (en) 2002-09-06

Family

ID=24656841

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/026647 WO2002023601A2 (en) 2000-09-14 2001-08-27 Method for contact etching using a hardmask and advanced resist technology

Country Status (1)

Country Link
WO (1) WO2002023601A2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5759746A (en) * 1996-05-24 1998-06-02 Kabushiki Kaisha Toshiba Fabrication process using a thin resist
JPH10289952A (en) * 1997-04-16 1998-10-27 Sony Corp Method of manufacturing semiconductor device
US5882996A (en) * 1997-10-14 1999-03-16 Industrial Technology Research Institute Method of self-aligned dual damascene patterning using developer soluble arc interstitial layer
US6030541A (en) * 1998-06-19 2000-02-29 International Business Machines Corporation Process for defining a pattern using an anti-reflective coating and structure therefor
US6107177A (en) * 1999-08-25 2000-08-22 Siemens Aktienesellschaft Silylation method for reducing critical dimension loss and resist loss

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5759746A (en) * 1996-05-24 1998-06-02 Kabushiki Kaisha Toshiba Fabrication process using a thin resist
JPH10289952A (en) * 1997-04-16 1998-10-27 Sony Corp Method of manufacturing semiconductor device
US5882996A (en) * 1997-10-14 1999-03-16 Industrial Technology Research Institute Method of self-aligned dual damascene patterning using developer soluble arc interstitial layer
US6030541A (en) * 1998-06-19 2000-02-29 International Business Machines Corporation Process for defining a pattern using an anti-reflective coating and structure therefor
US6107177A (en) * 1999-08-25 2000-08-22 Siemens Aktienesellschaft Silylation method for reducing critical dimension loss and resist loss

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 01 29 January 1999 (1999-01-29) *

Also Published As

Publication number Publication date
WO2002023601A2 (en) 2002-03-21

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