WO2002023353A2 - Apparatus for implementing a buffered daisy-chain ring connection between a memory controller and memory modules - Google Patents
Apparatus for implementing a buffered daisy-chain ring connection between a memory controller and memory modules Download PDFInfo
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- WO2002023353A2 WO2002023353A2 PCT/US2001/029236 US0129236W WO0223353A2 WO 2002023353 A2 WO2002023353 A2 WO 2002023353A2 US 0129236 W US0129236 W US 0129236W WO 0223353 A2 WO0223353 A2 WO 0223353A2
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
- G06F13/4256—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using a clocked protocol
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to memory systems in computer systems. More specifically, the present invention relates to an apparatus for implementing a buffered daisy chain ring connection between a memory controller and memory modules.
- DIMMs such as the Dual In-Line Memory Module (DIMM) have become a popular memory packaging design.
- DIMMs are small printed circuit boards mounted with a plurality of memory devices. DIMMs have leads accessible via both sides of a printed circuit board's electrical connector unlike its predecessor, the Single In-Line Memory Module (SIMM), which has leads on only one side of the printed circuit board's electrical connector. DIMMs are inserted into small socket connectors that are soldered • onto a larger printed circuit board, or motherboard.
- a plural number of memory modules are usually typically directly connected to a memory controller via multi-drop connections to a memory bus that is coupled to the memory side of the memory controller. The memory controller transmits and receives memory data via the memory bus.
- Each of the memory modules includes a plurality of memory devices mounted on the memory module.
- the memory devices typically are Dynamic Random Access Memory (DRAM).
- DRAM Dynamic Random Access Memory
- Figure 3 illustrates an end on view of a conventional multi-drop routing between a memory controller 111 and two exemplary memory modules 210-211.
- the memory bus 310 connects to each of the memory devices 210a and 210b through a stub.
- Stub 310a connects the bus 310 to memory devices 310a.
- Stub 310b connects the bus 310 to memory devices 21 lb.
- the stub introduces a capacitive load discontinuities to the signal being carried to the memory devices 21 la and 21 lb by the bus 310.
- the stubs directly connect to the memoiy devices without any intermediary signal conditioning including a voltage translation.
- a drawback to memory modules directly connected to a memory bus via multidrop connections is that there is no voltage level isolation between the memory devices and the memory controller. This lack of voltage isolation does not permit a variance between the voltage level of memory device inputs and memory controller outputs on the one hand, and memoiy device outputs and memory controller inputs on the other hand. Thus, in a system in which the signal level of a memory controller is below the memory device permissible range, the memory device will not recognize inputs, and memory device outputs will exceed the safe operating level of the memory controller or a coupled CPU.
- a memory module includes at least one memory device and a junction circuit.
- the junction circuit has a first port to couple to a bus from alternatively a memory controller and a daisy-chained other memory module.
- the junction circuits has a second port coupled to the memory devices, and a third port to couple to a bus from alternatively a memory controller or a daisy-chained other memory module.
- the junction circuit sends data received from the first port to the second port and i the third port, sends data received from the second port to the first port and the third port, and send data received from the third port to the second port and the first port.
- the junction circuit also includes an isolation circuit to provide a point-to-point connection to the first port and the third port, and a data synchronization circuit in electrical communication with the first port, the second port, and the third port to synchronize the data input to the first port with the data input to the third port.
- Figure 1 is a block diagram of a computer system implementing an embodiment of the present invention
- Figure 2 illustrates a memory system mounted on a motherboard according to an embodiment of the present invention
- Figure 3 illustrates an end on view of a conventional multi-drop routing between a memory controller and two exemplary memory modules;
- Figure 4 illustrates a bus routing and wiring topology for a memory system according to an embodiment of the present invention
- Figure 5 illustrates a junction circuit according to an embodiment of the present invention.
- Figure 1 illustrates a computer system 100 upon which an embodiment of the present invention can be implemented.
- the computer system 100 includes a processor 101 that processes data signals.
- the processor 101 may be a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or other processor device.
- Figure 1 shows an example of the present invention implemented on a single processor computer system 100. However, it is understood that the present invention may be implemented in a computer system having multiple processors.
- the processor 101 is coupled to a central processing unit CPU bus 110 that transmits data signals between processor 101 and other components in the computer system 100.
- the computer system 100 includes a memory system 113.
- the memory system 113 may include a dynamic random access memory (DRAM) device, a synchronous direct random access memory (SDRAM) device, a double data rate (DDR) SDRAM, a quad data rate (QDR) SDRAM a D 3 DDR SDRAM or other memory device (not shown).
- the memory system 113 may store instructions and code represented by data signals that may be executed by the processor 101.
- the memory system 113 comprises a plurality of memory modules 210-212 (portrayed in Figure 2), portrayed as an exemplary three memory modules. Each printed circuit board generally operates as a daughter card insertable into a socket connector that is connected to the computer system 100.
- a bridge memory controller 111 is coupled to the CPU bus 110 and the memory 113.
- the bridge memory controller 111 directs data signals between the processor 101, the memory system 113, and other components in the computer system 100 and bridges the data signals between the CPU bus 110, the memory system 113, and a first I/O bus 120.
- the processor 101, CPU bus 110, bridge/memory controller 111, and memory system 113 are together generally mounted on a common motherboard and are collectively referred to as the computer chipset 200 portrayed with reference to Figure 2.
- the first I/O bus 120 may be a single bus or a combination of multiple buses.
- the first I/O bus 120 may comprise a Peripheral Component Interconnect
- the first I/O bus 120 provides communication links between components in the computer system 100.
- a network controller 121 is coupled to the first I/O bus 120.
- the network controller 121 links the computer system 100 to a network of computers (not shown in Figure 1) and supports communication among the machines.
- a display device controller 122 is coupled to the first I/O bus 120.
- the display device controller 122 allows coupling of a display device (not shown) to the computer system 100 and acts as an interface between the display device and the computer system 100.
- the display device controller 122 may be a monochrome display adapter (MDA) card, a color graphics adapter (CGA) card, an enhanced graphics adapter (EGA) card, an extended graphics array (XGA) card or other display device controller.
- MDA monochrome display adapter
- CGA color graphics adapter
- EGA enhanced graphics adapter
- XGA extended graphics array
- the display device may be a television set, a computer monitor, a flat panel display or other display device.
- the display device receives data signals from the processor 101 through the display device controller 122 and displays the information and data signals to the user of the computer system 100.
- a video camera 123 is coupled to the first I/O bus 120.
- a second I/O bus 130 may be a single bus or a combination of multiple buses.
- the second I/O bus 130 may comprise a PCI bus, a PCMCIA bus, a NuBus, an Industry Standard Architecture (ISA) bus, or other buses.
- the second I/O bus 130 provides communication links between components in the computer system 100.
- a data storage device 131 is coupled to the second I/O bus 130.
- the data storage device 131 may be a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device or other mass storage device.
- a keyboard interface 132 is coupled to the second I/O bus 130.
- the keyboard interface 132 may be a keyboard controller or other keyboard interface.
- the keyboard interface 132 may be a dedicated device or can reside in another device such as a bus controller or other controller.
- the keyboard interface 132 allows coupling of a keyboard (not shown) to the computer system 100 and transmits data signals from a keyboard to the computer system 100.
- An audio controller 133 is coupled to the second I/O bus 130.
- the audio controller 133 operates to coordinate the recording and playing of sounds is also coupled to the I/O bus 130.
- a bus bridge 124 couples the first I/O bus 120 to the second I/O bus 130.
- the bus bridge 124 operates to buffer and bridge data signals between the first I/O bus 120 and the second I/O bus 130.
- FIG. 2 illustrates a memory system 113 according to an embodiment of the present invention.
- the memory system 113 generally resides on a motherboard 200 of the computer system 100.
- the motherboard 200 is a printed circuit board that interconnects components of the computer system 100 such as the bridge memory controller 111, the processor 101 and other components.
- the memory system 113 includes a plurality of memory modules 210-212. Each of the memory modules 210- 212 comprises a printed circuit board 210a-212a mounting a plurality of memory devices 210b-212b.
- the memory system also generally includes a plurality of socket connectors 220-222 mounted on the motherboard 200.
- the memory modules 210-212 are insertable into the socket connectors 220-222. Electrical connectors on the memory module interface with electrical contacts in the socket connector.
- the electrical connectors and the electrical contacts allow components on the motherboard 200 to access the memory devices on the memory module. It should be appreciated that any number of socket connectors may be mounted on the motherboard to receive any number of memory modules. It should also be appreciated that any number of memory devices may be mounted on each memory module.
- the memory system 113 may be implemented in a computer system which partitions I/O structures differently than the one illustrated in Figure 1.
- Figure 4 illustrates a bus routing and topology for the present invention for an embodiment having more than one memory modules, here portrayed as daisy-chained memory modules 310a and 310b, wherein each memory module is connected in a daisy- chain according to the interfaces portrayed herein, and wherein the daisy-chained memory modules 310a and 310b are connected in a ring with the memory controller 111.
- the first memory module 310a in the daisy-chain is connected on a first port 314a to the memory controller 111 via a separate bus 320
- the last memory module 310b in the daisy-chain is connected on a third port 315b to the memory controller 111 via a separate bus 330.
- the bus 320 transmits and receives to and from the memory modules in the daisy-chain a first set of data including at least one of at least one memory-data line and one non-memory data line.
- the bus 330 data transmits and receives to and from the memory modules in the daisy-chain a second set of data including at least one of at least one memory-data line and one non-memory data line.
- the non-memory data signals may include at least one of address lines, command lines, and clock lines.
- the memory module 310a includes the junction circuit 312a, also referred to as a buffer.
- the bus 320 is coupled to a first port 314a of the junction circuit 312a.
- the junction circuit 312a is coupled to memory devices 31 la by a bus from port 313a of junction circuit 312a to port 316a of the memory devices 31 la, wherein the port 316a is representative of each of the separate memory devices that populate the memory module 311a.
- the junction circuit 312a is further coupled by a bus 325 between a port 315a of the junction circuit 312a to a port 314b of the junction circuit 312b.
- the data input to the junction circuit 312a from bus 320 is routed by the junction circuit 312a to port 315a and transmitted through bus 325 to junction circuit 312b.
- the data input to the junction circuit 312a on port 315a from the junction circuit 312b is routed through port 315a to the bus 320.
- the memory module 310b includes the junction circuit 312b.
- Thejunction circuit 320b is coupled by a bus from a port 313b to the memory devices 311b, wherein the port 316b is representative of each of the separate memory devices that populate the memory module 310b.
- the data input to thejunction circuit 312b at port 314b from junction circuit 312a is routed by thejunction circuit 312b to port 315b and transmitted via bus 330 to the memory controller 111.
- the data input to the junction circuit 312b from the memory controller 111 via bus 330 is input and routed through port 315b to the bus 325.
- the data transmitted to and from junction circuit 312b is routed through bus 330 to and from the memory controller 111.
- the data transmitted from the memory devices 311a and 31 lb are routed through bus 320 for data conforming to the first set of data, and are routed through bus 330 for data conforming to the second set of data.
- FIG. 5 is a block diagram of a junction circuit 500 also referred to as a buffer according to an embodiment of the present invention.
- the junction circuit 500 includes other circuitry well known in the art such as signal regeneration circuitry and signal synchronization circuitry.
- Each of blocks 510, 520, 530, and 540 represents, a separate circuit function of the present invention. However, it is understood that more than one function can be performed by the same circuit elements, such as a voltage translation circuit can also provide a capacitive isolation to a signal line.
- the sequence of process functions represented by the blocks 510, 520, 530, and 540 may be varied.
- block 530 represents a voltage translation circuit that includes both a voltage raising function and a voltage lowering function
- the voltage raising circuitry and the voltage lowering circuit include separate circuitry that can each be coupled in different positions in the data path.
- block 540 represents a multiplexing/de-multiplexing function that includes both a multiplexing function and a de-multiplexing function
- the multiplexing circuit and the demultiplexing circuit include separate circuitry that can each be coupled in different positions in the data path. It is preferred that the de-multiplexing function represented by multiplexing/demultiplexing block 540 be performed after the voltage translation function represented by block 530, and that the multiplexing function represented by block 540 be performed before the voltage translation function represented by block 530.
- the demultiplexing functions translates an input signal on a given number of lines into an output signal on a greater number of lines
- the multiplexing function translates an input signal on a given number of lines into an output signal on a lesser number of lines.
- the voltage translation function represented by block 530 to raise the data signal to a level in accordance with the requirements of memory devices can be performed on the data signal carried by bus 503a by performing a voltage raising function represented by block 530 on the data signal before it is ported out to bus 503a, then the voltage of the data signal carried by bus 503a must then be lowered by the voltage translation function represented by block 530 by placement of voltage lowering circuitry in the bus 503a data path.
- a memory bus 550 couples to thejunction circuit 500 at port 501.
- the memory bus 550 includes a plurality of lines that includes at least one of at least one memory-data lines and at least one non-memory data lines that may include addressing lines, command lines, and clock lines, and that shall be referred to hereafter as ADD/CMD lines.
- the memory bus 550 transmits to thejunction circuit 500 (and other memoiy devices on other memory modules (not shown) and the memory controller (not shown)) a first set of data lines.
- the memory bus 550 receives from thejunction circuit 500 (and other memory modules (not shown) and the memory controller (not shown)) data for a second set data lines.
- the preferred embodiment first set of data lines and second set of data lines are exclusive and together constitutes the total data lines needed for the memory devices 560.
- 'A memory bus 570 couples to the junction circuit at port 503.
- the memory bus 570 couples to the junction circuit at port 503.
- the memory bus 570 couples to the junction circuit at port 503.
- the memory bus 570 couples to the junction circuit at port
- the 550 includes a plurality of lines that includes at least one of at least one memory-data lines and at least one ADD/CMD lines.
- the memory bus 570 transmits to thejunction circuit 500 (and other memory devices on other memory modules (not shown) and the memory controller (not shown)) a third set of data lines (not shown).
- the memory bus 550 receives from thejunction circuit 500 (and other memory modules (not shown) and the memory controller (not shown)) data for a fourth set data lines (not shown).
- the preferred embodiment third set of data lines and fourth set of data lines are exclusive and together constitutes the total data lines needed for the memory devices 560.
- the first data set, second data set, third data set, and fourth data together constitute a transmission and a reception of the total data lines needed for the memory devices 560 (and all other data devices in the ring).
- the bus lines 550 and 570 are each coupled to a capacitive isolation circuit represented by block 510 to isolate thejunction circuit 500 from the buses 550 and 570, resulting in a point to point connection between the junction circuit 500 and the other memory modules and memory controller on the ring topology daisy chain, rather than the conventional multi-drop configuration for a circuit having a plurality of memory modules as portrayed with reference to Figure 3.
- the data transmitted to thejunction circuit 500 from the bus 570 is routed to bus 503a and transmitted on bus 570 to a port 501 of a daisy- chained junction circuit.
- the data from the daisy-chained junction circuit is received by junction circuit 500 on bus 570 at port 503, and routed to the port 501 to the bus 550.
- the capacitive isolation circuit 510 provides a termination for the bus 550 and allows the bus 550 to achieve much higher frequencies due to very limited impedance discontinuities on the bus 550. Impedance discontinuities cause reflections in the waveform limiting the maximum frequency on the bus 550. With lower discontinuities on the bus, the frequency of the bus can be increased to a much higher rate over existing multi-drop memory buses.
- the isolation circuit 510 is coupled to both a data synchronization circuit 520 via bus 510a, and an output port 503 via bus 503a.
- the bus 510a for the purpose of this embodiment transmits data to the data synchronization circuit 520 for the memory devices 560.
- the synchronization circuit 520 synchronized the data received from the bus 550 with the data received from the bus 570, because the total data transmission from bus 550 and 570 constitutes the total data signal to the memoiy devices 560. Because the data from bus 550 and from bus 570 each pass through a not necessarily equal number of memory modules (if any) before reception by the memory junction circuit 500, they arrive at different times because there is at least a one clock delay to transit a memory module.
- the data synchronization circuit synchronizes the two data streams depending upon the difference in arrival time caused by the number of intermediate other memory modules the data input to ports 501 and 503 each pass through before input to thejunction circuit 500, and transmit the synchronized data to the memory devices through the voltage translation circuit in this embodiment.
- the bus 510b for the purpose of this embodiment transmits data from the memory devices to the isolation circuit 510, because a synchronization is preferably applied only to the data transmitted to the memory devices 560.
- the bus 520a for the purpose of this embodiment transmits data to the voltage translation circuit 530 for the memory devices 560, and the bus 510b transmits data to the isolation circuit 510 from the memory devices 560.
- the voltage translation function 530 includes a voltage raising circuit to translate the voltage range of each separate signal input to the junction circuit 500 from bus 550 (dependent upon the position of the demultiplexing circuit) from a range commensurate with a transmission from a memory controller or CPU, to a range commensurate with an input to the memoiy devices 560.
- the voltage translation function 530 includes a voltage lowering circuit to translate the voltage range of each separate signal output from the memory devices (dependent upon the position of the multiplexing circuit) from a range commensurate with a transmission from a memory device, to a range commensurate with an input to a memory controller or a CPU.
- the bus 530a for the purpose of this embodiment transmits data to the demultiplexing circuit of the multiplexing/de-multiplexing function 540 from the voltage translation function 530 and from the multiplexing circuit of the multiplexing/demultiplexing function 540 to the voltage translation function 530.
- the de-multiplexing circuit processes an input having n lines, and de-multiplexes the input so that the output has m lines, wherein n is less than m (where m and n can be expressed alternatively as p and q).
- n is less than m (where m and n can be expressed alternatively as p and q).
- the input bit rate on each line is decreased by a ratio of n/m to maintain the same bandwidth on the input side as on the output side of the de-multiplexer circuit.
- the present invention enables a smaller number of data lines input to thejunction circuit 500 than the memory devices 560 require allowing a narrower connecting bus 550 and 570. Moreover, because only a portion of the data is received and transmitted on each bus 550 and 570, each of the buses may have a lower bandwidth and a smaller number of lines than would otherwise be necessary. This lowers the number of required pins on the memory module 560. Furthermore, the present invention enables lower frequencies on the input bus 501, thus decreases the power lost to capacitive load.
- the bus 540a for the purpose of this embodiment transmits data from thejunction circuit port 502 to the multiplexing circuit of the multiplexing/de-multiplexing function 540, and transmits data from the de-multiplexing circuit of the multiplexer/de-multiplexer function 540 to the junction circuit port 502.
- the multiplexing circuit processes an input having m lines, and de-multiplexes the input so that the output has n lines, wherein n is less than m.
- the output bit rate on each line is increased by a ratio of m/n to maintain the same bandwidth on the input side as on the output side of the multiplexer circuit.
- the present invention enables a smaller number of data lines input to the junction circuit 500 than the memory devices 560 require. This lowers the number of required pins on the memory module.
- the present invention enables a lower frequencies on the input bus 501, thus decreased the power lost to capacitive load.
- junction circuit port 502 data is input and output to the memory devices 560 over the individual buses 560a-560h, and ADD/CMD data is input to the memory devices over the bus 560i.
- ADD/CMD data is input to the memory devices over the bus 560i.
- the need to signal condition individual ADD/CMD lines, and to signal condition memory data lines is different because of the possible differing requirements with regard to voltage translation and multiplexing/demultiplexing. Accordingly, it is specifically contemplated that different multiplexer, de- multiplexer, and voltage translation circuits will be used for each.
- different embodiments of the present invention may not apply the isolation functions, the voltage translation functions, or the multiplexing/de-multiplexing functions to both the memory- data and the ADD/CMD data.
- an embodiment of the present invention may not include the CMD/ADD data being transmitted from a junction circuit 500 from a port 501, and accordingly will not require the isolation function, the voltage lowering function, and the multiplexing function to a return ADD/CMD signal.
- a preferred embodiment includes two physically separate memory-data processing circuits, each memory-data circuit coupled to an exclusive subset of the memory devices 560, and one physically separate ADD/CMD processing circuit, each circuit including according to the embodiment the voltage translation, the isolation, and the multiplexing/de-multiplexing circuits.
- the two separate memory data-circuits enabling a data line topology that is more straightforward than would be the case with a unitary device.
Abstract
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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AU2001292776A AU2001292776A1 (en) | 2000-09-18 | 2001-09-18 | Apparatus for implementing a buffered daisy-chain ring connection between a memory controller and memory modules |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/665,238 | 2000-09-18 | ||
US09/665,238 US6625687B1 (en) | 2000-09-18 | 2000-09-18 | Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing |
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WO2002023353A2 true WO2002023353A2 (en) | 2002-03-21 |
WO2002023353A3 WO2002023353A3 (en) | 2003-07-31 |
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PCT/US2001/029236 WO2002023353A2 (en) | 2000-09-18 | 2001-09-18 | Apparatus for implementing a buffered daisy-chain ring connection between a memory controller and memory modules |
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US (1) | US6625687B1 (en) |
AU (1) | AU2001292776A1 (en) |
TW (1) | TWI223151B (en) |
WO (1) | WO2002023353A2 (en) |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6625687B1 (en) * | 2000-09-18 | 2003-09-23 | Intel Corporation | Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing |
EP1429340A2 (en) * | 2002-12-12 | 2004-06-16 | Samsung Electronics Co., Ltd. | Memory system having two-way ring topology and memory device and memory module for ring topology memory system |
JP2004192616A (en) * | 2002-12-12 | 2004-07-08 | Samsung Electronics Co Ltd | Memory system, memory device and memory module |
WO2004102403A2 (en) * | 2003-05-13 | 2004-11-25 | Advanced Micro Devices, Inc. | A system including a host connected to a plurality of memory modules via a serial memory interconnect |
EP1628225A2 (en) * | 2004-07-30 | 2006-02-22 | International Business Machines Corporation | Bus speed multiplier in a memory subsystem |
EP1769361A2 (en) * | 2004-05-28 | 2007-04-04 | Micron Technology, Inc. | Method and system for terminating write commands in a hub-based memory system |
DE102006006571A1 (en) * | 2006-02-13 | 2007-08-16 | Infineon Technologies Ag | Semiconductor arrangement and method for operating a semiconductor device |
US7669086B2 (en) | 2006-08-02 | 2010-02-23 | International Business Machines Corporation | Systems and methods for providing collision detection in a memory system |
US7685392B2 (en) | 2005-11-28 | 2010-03-23 | International Business Machines Corporation | Providing indeterminate read data latency in a memory system |
US7721140B2 (en) | 2007-01-02 | 2010-05-18 | International Business Machines Corporation | Systems and methods for improving serviceability of a memory system |
US7765368B2 (en) | 2004-07-30 | 2010-07-27 | International Business Machines Corporation | System, method and storage medium for providing a serialized memory interface with a bus repeater |
US7788451B2 (en) | 2004-02-05 | 2010-08-31 | Micron Technology, Inc. | Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system |
US7844771B2 (en) | 2004-10-29 | 2010-11-30 | International Business Machines Corporation | System, method and storage medium for a memory subsystem command interface |
US7870459B2 (en) | 2006-10-23 | 2011-01-11 | International Business Machines Corporation | High density high reliability memory module with power gating and a fault tolerant address and command bus |
US7873775B2 (en) | 2003-08-28 | 2011-01-18 | Round Rock Research, Llc | Multiple processor system and method including multiple memory hub modules |
US8082404B2 (en) | 2004-03-24 | 2011-12-20 | Micron Technology, Inc. | Memory arbitration system and method having an arbitration packet protocol |
US8140942B2 (en) | 2004-10-29 | 2012-03-20 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
US8164375B2 (en) | 2004-04-05 | 2012-04-24 | Round Rock Research, Llc | Delay line synchronizer apparatus and method |
US8589643B2 (en) | 2003-10-20 | 2013-11-19 | Round Rock Research, Llc | Arbitration system and method for memory responses in a hub-based memory system |
Families Citing this family (101)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6643752B1 (en) | 1999-12-09 | 2003-11-04 | Rambus Inc. | Transceiver with latency alignment circuitry |
US6502161B1 (en) | 2000-01-05 | 2002-12-31 | Rambus Inc. | Memory system including a point-to-point linked memory subsystem |
US7266634B2 (en) * | 2000-01-05 | 2007-09-04 | Rambus Inc. | Configurable width buffered module having flyby elements |
US7356639B2 (en) * | 2000-01-05 | 2008-04-08 | Rambus Inc. | Configurable width buffered module having a bypass circuit |
US7363422B2 (en) * | 2000-01-05 | 2008-04-22 | Rambus Inc. | Configurable width buffered module |
US20050010737A1 (en) * | 2000-01-05 | 2005-01-13 | Fred Ware | Configurable width buffered module having splitter elements |
US7017002B2 (en) * | 2000-01-05 | 2006-03-21 | Rambus, Inc. | System featuring a master device, a buffer device and a plurality of integrated circuit memory devices |
US6889304B2 (en) | 2001-02-28 | 2005-05-03 | Rambus Inc. | Memory device supporting a dynamically configurable core organization |
US7610447B2 (en) * | 2001-02-28 | 2009-10-27 | Rambus Inc. | Upgradable memory system with reconfigurable interconnect |
US6877079B2 (en) * | 2001-03-06 | 2005-04-05 | Samsung Electronics Co., Ltd. | Memory system having point-to-point bus configuration |
US6882082B2 (en) * | 2001-03-13 | 2005-04-19 | Micron Technology, Inc. | Memory repeater |
US6825841B2 (en) * | 2001-09-07 | 2004-11-30 | Rambus Inc. | Granularity memory column access |
US6938129B2 (en) * | 2001-12-31 | 2005-08-30 | Intel Corporation | Distributed memory module cache |
US7110400B2 (en) * | 2002-04-10 | 2006-09-19 | Integrated Device Technology, Inc. | Random access memory architecture and serial interface with continuous packet handling capability |
JP4159415B2 (en) | 2002-08-23 | 2008-10-01 | エルピーダメモリ株式会社 | Memory module and memory system |
KR100468761B1 (en) * | 2002-08-23 | 2005-01-29 | 삼성전자주식회사 | Semiconductor memory system having memory module connected to devided system bus |
US7080222B1 (en) * | 2002-09-20 | 2006-07-18 | Cypress Semiconductor Corp. | Cellular telephone memory with backup memory interface |
US7362697B2 (en) * | 2003-01-09 | 2008-04-22 | International Business Machines Corporation | Self-healing chip-to-chip interface |
US7200787B2 (en) * | 2003-06-03 | 2007-04-03 | Intel Corporation | Memory channel utilizing permuting status patterns |
US7194581B2 (en) * | 2003-06-03 | 2007-03-20 | Intel Corporation | Memory channel with hot add/remove |
US7127629B2 (en) * | 2003-06-03 | 2006-10-24 | Intel Corporation | Redriving a data signal responsive to either a sampling clock signal or stable clock signal dependent on a mode signal |
US8171331B2 (en) | 2003-06-04 | 2012-05-01 | Intel Corporation | Memory channel having deskew separate from redrive |
US7340537B2 (en) * | 2003-06-04 | 2008-03-04 | Intel Corporation | Memory channel with redundant presence detect |
US7165153B2 (en) | 2003-06-04 | 2007-01-16 | Intel Corporation | Memory channel with unidirectional links |
US7386768B2 (en) | 2003-06-05 | 2008-06-10 | Intel Corporation | Memory channel with bit lane fail-over |
US7243205B2 (en) * | 2003-11-13 | 2007-07-10 | Intel Corporation | Buffered memory module with implicit to explicit memory command expansion |
US7177211B2 (en) * | 2003-11-13 | 2007-02-13 | Intel Corporation | Memory channel test fixture and method |
US7219294B2 (en) * | 2003-11-14 | 2007-05-15 | Intel Corporation | Early CRC delivery for partial frame |
US7143207B2 (en) * | 2003-11-14 | 2006-11-28 | Intel Corporation | Data accumulation between data path having redrive circuit and memory device |
US7447953B2 (en) | 2003-11-14 | 2008-11-04 | Intel Corporation | Lane testing with variable mapping |
JP2005190036A (en) * | 2003-12-25 | 2005-07-14 | Hitachi Ltd | Storage controller and control method for storage controller |
US8250295B2 (en) * | 2004-01-05 | 2012-08-21 | Smart Modular Technologies, Inc. | Multi-rank memory module that emulates a memory module having a different number of ranks |
US7289386B2 (en) | 2004-03-05 | 2007-10-30 | Netlist, Inc. | Memory module decoder |
US7532537B2 (en) * | 2004-03-05 | 2009-05-12 | Netlist, Inc. | Memory module with a circuit providing load isolation and memory domain translation |
US7916574B1 (en) | 2004-03-05 | 2011-03-29 | Netlist, Inc. | Circuit providing load isolation and memory domain translation for memory module |
US7212423B2 (en) * | 2004-05-31 | 2007-05-01 | Intel Corporation | Memory agent core clock aligned to lane |
JP4610235B2 (en) * | 2004-06-07 | 2011-01-12 | ルネサスエレクトロニクス株式会社 | Hierarchical module |
US20060004953A1 (en) * | 2004-06-30 | 2006-01-05 | Vogt Pete D | Method and apparatus for increased memory bandwidth |
US7383399B2 (en) * | 2004-06-30 | 2008-06-03 | Intel Corporation | Method and apparatus for memory compression |
US7389375B2 (en) * | 2004-07-30 | 2008-06-17 | International Business Machines Corporation | System, method and storage medium for a multi-mode memory buffer device |
US7224595B2 (en) | 2004-07-30 | 2007-05-29 | International Business Machines Corporation | 276-Pin buffered memory module with enhanced fault tolerance |
US8375146B2 (en) * | 2004-08-09 | 2013-02-12 | SanDisk Technologies, Inc. | Ring bus structure and its use in flash memory systems |
US8190808B2 (en) * | 2004-08-17 | 2012-05-29 | Rambus Inc. | Memory device having staggered memory operations |
US7254075B2 (en) * | 2004-09-30 | 2007-08-07 | Rambus Inc. | Integrated circuit memory system having dynamic memory bank count and page size |
US7280428B2 (en) | 2004-09-30 | 2007-10-09 | Rambus Inc. | Multi-column addressing mode memory system including an integrated circuit memory device |
US7512762B2 (en) | 2004-10-29 | 2009-03-31 | International Business Machines Corporation | System, method and storage medium for a memory subsystem with positional read data latency |
US7356737B2 (en) * | 2004-10-29 | 2008-04-08 | International Business Machines Corporation | System, method and storage medium for testing a memory module |
US7305574B2 (en) * | 2004-10-29 | 2007-12-04 | International Business Machines Corporation | System, method and storage medium for bus calibration in a memory subsystem |
US7277988B2 (en) * | 2004-10-29 | 2007-10-02 | International Business Machines Corporation | System, method and storage medium for providing data caching and data compression in a memory subsystem |
US7395476B2 (en) * | 2004-10-29 | 2008-07-01 | International Business Machines Corporation | System, method and storage medium for providing a high speed test interface to a memory subsystem |
US8595459B2 (en) | 2004-11-29 | 2013-11-26 | Rambus Inc. | Micro-threaded memory |
US20060164909A1 (en) * | 2005-01-24 | 2006-07-27 | International Business Machines Corporation | System, method and storage medium for providing programmable delay chains for a memory system |
KR100666225B1 (en) * | 2005-02-17 | 2007-01-09 | 삼성전자주식회사 | Multi device system forming daisy chain and operating method for the same |
US20060248305A1 (en) * | 2005-04-13 | 2006-11-02 | Wayne Fang | Memory device having width-dependent output latency |
US7545651B2 (en) * | 2005-04-18 | 2009-06-09 | Hewlett-Packard Development Company, L.P. | Memory module with a predetermined arrangement of pins |
US9582449B2 (en) | 2005-04-21 | 2017-02-28 | Violin Memory, Inc. | Interconnection system |
US8112655B2 (en) | 2005-04-21 | 2012-02-07 | Violin Memory, Inc. | Mesosynchronous data bus apparatus and method of data transmission |
KR101331569B1 (en) | 2005-04-21 | 2013-11-21 | 바이올린 메모리 인코포레이티드 | Interconnection System |
US9286198B2 (en) | 2005-04-21 | 2016-03-15 | Violin Memory | Method and system for storage of data in non-volatile media |
US8452929B2 (en) | 2005-04-21 | 2013-05-28 | Violin Memory Inc. | Method and system for storage of data in non-volatile media |
US9384818B2 (en) | 2005-04-21 | 2016-07-05 | Violin Memory | Memory power management |
KR100723486B1 (en) * | 2005-05-12 | 2007-05-30 | 삼성전자주식회사 | Memory module having SIMM/DIMM structure and memory system |
US20060277355A1 (en) * | 2005-06-01 | 2006-12-07 | Mark Ellsberry | Capacity-expanding memory device |
US7562271B2 (en) | 2005-09-26 | 2009-07-14 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US11328764B2 (en) | 2005-09-26 | 2022-05-10 | Rambus Inc. | Memory system topologies including a memory die stack |
US7464225B2 (en) | 2005-09-26 | 2008-12-09 | Rambus Inc. | Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology |
US7478259B2 (en) | 2005-10-31 | 2009-01-13 | International Business Machines Corporation | System, method and storage medium for deriving clocks in a memory system |
US7477526B1 (en) | 2005-12-29 | 2009-01-13 | Co Ramon S | Branching fully-buffered memory-module with two downlink and one uplink ports |
US7739474B2 (en) * | 2006-02-07 | 2010-06-15 | International Business Machines Corporation | Method and system for unifying memory access for CPU and IO operations |
US7404055B2 (en) | 2006-03-28 | 2008-07-22 | Intel Corporation | Memory transfer with early access to critical portion |
US7389381B1 (en) | 2006-04-05 | 2008-06-17 | Co Ramon S | Branching memory-bus module with multiple downlink ports to standard fully-buffered memory modules |
US20070260841A1 (en) | 2006-05-02 | 2007-11-08 | Hampel Craig E | Memory module with reduced access granularity |
US7636813B2 (en) * | 2006-05-22 | 2009-12-22 | International Business Machines Corporation | Systems and methods for providing remote pre-fetch buffers |
US7584336B2 (en) * | 2006-06-08 | 2009-09-01 | International Business Machines Corporation | Systems and methods for providing data modification operations in memory subsystems |
US7581073B2 (en) * | 2006-08-09 | 2009-08-25 | International Business Machines Corporation | Systems and methods for providing distributed autonomous power management in a memory system |
US7970990B2 (en) * | 2006-09-22 | 2011-06-28 | Oracle America, Inc. | Memory module with optical interconnect that enables scalable high-bandwidth memory access |
US7477522B2 (en) * | 2006-10-23 | 2009-01-13 | International Business Machines Corporation | High density high reliability memory module with a fault tolerant address and command bus |
US8028186B2 (en) | 2006-10-23 | 2011-09-27 | Violin Memory, Inc. | Skew management in an interconnection system |
EP3279798B1 (en) | 2007-03-30 | 2020-07-29 | Rambus Inc. | System including hierarchical memory modules having different types of integrated circuit memory devices |
US8315269B1 (en) * | 2007-04-18 | 2012-11-20 | Cypress Semiconductor Corporation | Device, method, and protocol for data transfer between host device and device having storage interface |
US20090043946A1 (en) * | 2007-08-09 | 2009-02-12 | Webb Randall K | Architecture for very large capacity solid state memory systems |
TWI448902B (en) | 2007-08-24 | 2014-08-11 | Cypress Semiconductor Corp | Bridge device with page-access based processor interface |
US8090894B1 (en) | 2007-09-21 | 2012-01-03 | Cypress Semiconductor Corporation | Architectures for supporting communication and access between multiple host devices and one or more common functions |
US8825939B2 (en) * | 2007-12-12 | 2014-09-02 | Conversant Intellectual Property Management Inc. | Semiconductor memory device suitable for interconnection in a ring topology |
US8417870B2 (en) | 2009-07-16 | 2013-04-09 | Netlist, Inc. | System and method of increasing addressable memory space on a memory board |
US8516185B2 (en) | 2009-07-16 | 2013-08-20 | Netlist, Inc. | System and method utilizing distributed byte-wise buffers on a memory module |
US8154901B1 (en) | 2008-04-14 | 2012-04-10 | Netlist, Inc. | Circuit providing load isolation and noise reduction |
US8139390B2 (en) * | 2008-07-08 | 2012-03-20 | Mosaid Technologies Incorporated | Mixed data rates in memory devices and systems |
US10236032B2 (en) * | 2008-09-18 | 2019-03-19 | Novachips Canada Inc. | Mass data storage system with non-volatile memory modules |
US8856434B2 (en) * | 2008-09-26 | 2014-10-07 | Cypress Semiconductor Corporation | Memory system and method |
US8181056B2 (en) * | 2008-09-30 | 2012-05-15 | Mosaid Technologies Incorporated | Serial-connected memory system with output delay adjustment |
US8161313B2 (en) * | 2008-09-30 | 2012-04-17 | Mosaid Technologies Incorporated | Serial-connected memory system with duty cycle correction |
US8503211B2 (en) * | 2009-05-22 | 2013-08-06 | Mosaid Technologies Incorporated | Configurable module and memory subsystem |
US9128632B2 (en) | 2009-07-16 | 2015-09-08 | Netlist, Inc. | Memory module with distributed data buffers and method of operation |
US8582382B2 (en) * | 2010-03-23 | 2013-11-12 | Mosaid Technologies Incorporated | Memory system having a plurality of serially connected devices |
KR101796116B1 (en) | 2010-10-20 | 2017-11-10 | 삼성전자 주식회사 | Semiconductor device, memory module and memory system having the same and operating method thereof |
US9268719B2 (en) | 2011-08-05 | 2016-02-23 | Rambus Inc. | Memory signal buffers and modules supporting variable access granularity |
US9471484B2 (en) | 2012-09-19 | 2016-10-18 | Novachips Canada Inc. | Flash memory controller having dual mode pin-out |
CN110428855B (en) | 2013-07-27 | 2023-09-22 | 奈特力斯股份有限公司 | Memory module with local synchronization |
US10679722B2 (en) | 2016-08-26 | 2020-06-09 | Sandisk Technologies Llc | Storage system with several integrated components and method for use therewith |
TWI748205B (en) * | 2017-05-03 | 2021-12-01 | 大陸商合肥沛睿微電子股份有限公司 | Method for extending capacity of memory system |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4974152A (en) * | 1986-05-15 | 1990-11-27 | Yves Guiffant | Inserted device for independently connecting auxiliary storage units to a data-processing assembly |
US5448715A (en) * | 1992-07-29 | 1995-09-05 | Hewlett-Packard Company | Dual clock domain interface between CPU and memory bus |
US5828892A (en) * | 1996-02-27 | 1998-10-27 | Mitsubishi Denki Kabushiki Kaisha | Memory cards capable of operating with more than one power supply voltage |
US5859809A (en) * | 1996-12-31 | 1999-01-12 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device of daisy chain structure having independent refresh apparatus |
US6028781A (en) * | 1996-12-19 | 2000-02-22 | Texas Instruments Incorporated | Selectable integrated circuit assembly and method of operation |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5757712A (en) * | 1996-07-12 | 1998-05-26 | International Business Machines Corporation | Memory modules with voltage regulation and level translation |
US5831890A (en) * | 1996-12-16 | 1998-11-03 | Sun Microsystems, Inc. | Single in-line memory module having on-board regulation circuits |
JP3727778B2 (en) * | 1998-05-07 | 2005-12-14 | 株式会社東芝 | Data high-speed transfer synchronization system and data high-speed transfer synchronization method |
US6625687B1 (en) * | 2000-09-18 | 2003-09-23 | Intel Corporation | Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing |
US6317352B1 (en) * | 2000-09-18 | 2001-11-13 | Intel Corporation | Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules |
-
2000
- 2000-09-18 US US09/665,238 patent/US6625687B1/en not_active Expired - Lifetime
-
2001
- 2001-09-18 AU AU2001292776A patent/AU2001292776A1/en not_active Abandoned
- 2001-09-18 WO PCT/US2001/029236 patent/WO2002023353A2/en active Application Filing
- 2001-09-19 TW TW090123039A patent/TWI223151B/en not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4974152A (en) * | 1986-05-15 | 1990-11-27 | Yves Guiffant | Inserted device for independently connecting auxiliary storage units to a data-processing assembly |
US5448715A (en) * | 1992-07-29 | 1995-09-05 | Hewlett-Packard Company | Dual clock domain interface between CPU and memory bus |
US5828892A (en) * | 1996-02-27 | 1998-10-27 | Mitsubishi Denki Kabushiki Kaisha | Memory cards capable of operating with more than one power supply voltage |
US6028781A (en) * | 1996-12-19 | 2000-02-22 | Texas Instruments Incorporated | Selectable integrated circuit assembly and method of operation |
US5859809A (en) * | 1996-12-31 | 1999-01-12 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device of daisy chain structure having independent refresh apparatus |
Cited By (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6625687B1 (en) * | 2000-09-18 | 2003-09-23 | Intel Corporation | Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing |
US7093076B2 (en) | 2002-12-12 | 2006-08-15 | Samsung Electronics, Co., Ltd. | Memory system having two-way ring topology and memory device and memory module for ring-topology memory system |
EP1429340A2 (en) * | 2002-12-12 | 2004-06-16 | Samsung Electronics Co., Ltd. | Memory system having two-way ring topology and memory device and memory module for ring topology memory system |
JP2004192616A (en) * | 2002-12-12 | 2004-07-08 | Samsung Electronics Co Ltd | Memory system, memory device and memory module |
CN100440173C (en) * | 2002-12-12 | 2008-12-03 | 三星电子株式会社 | Bidirectional loop layout storing system, loop layout storing system memory device and memory module |
EP1429340A3 (en) * | 2002-12-12 | 2005-10-12 | Samsung Electronics Co., Ltd. | Memory system having two-way ring topology and memory device and memory module for ring topology memory system |
KR101095025B1 (en) * | 2003-05-13 | 2011-12-20 | 어드밴스드 마이크로 디바이시즈, 인코포레이티드 | A system including a host connected to a plurality of memory modules via a serial memory interconnect |
WO2004102403A2 (en) * | 2003-05-13 | 2004-11-25 | Advanced Micro Devices, Inc. | A system including a host connected to a plurality of memory modules via a serial memory interconnect |
GB2416056A (en) * | 2003-05-13 | 2006-01-11 | Advanced Micro Devices Inc | A system including a host connected to a plurality of memory modules via a serial memory interconnect |
GB2416056B (en) * | 2003-05-13 | 2006-08-23 | Advanced Micro Devices Inc | A system including a host connected to a plurality of memory modules via a serial memory interconnect |
US7421525B2 (en) | 2003-05-13 | 2008-09-02 | Advanced Micro Devices, Inc. | System including a host connected to a plurality of memory modules via a serial memory interconnect |
WO2004102403A3 (en) * | 2003-05-13 | 2005-08-25 | Advanced Micro Devices Inc | A system including a host connected to a plurality of memory modules via a serial memory interconnect |
CN100444141C (en) * | 2003-05-13 | 2008-12-17 | 先进微装置公司 | System including a host connected to a plurality of memory modules via a serial memory interconnet |
US7873775B2 (en) | 2003-08-28 | 2011-01-18 | Round Rock Research, Llc | Multiple processor system and method including multiple memory hub modules |
US8589643B2 (en) | 2003-10-20 | 2013-11-19 | Round Rock Research, Llc | Arbitration system and method for memory responses in a hub-based memory system |
US9164937B2 (en) | 2004-02-05 | 2015-10-20 | Micron Technology, Inc. | Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system |
US7788451B2 (en) | 2004-02-05 | 2010-08-31 | Micron Technology, Inc. | Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system |
US8555006B2 (en) | 2004-03-24 | 2013-10-08 | Micron Technology, Inc. | Memory arbitration system and method having an arbitration packet protocol |
US8082404B2 (en) | 2004-03-24 | 2011-12-20 | Micron Technology, Inc. | Memory arbitration system and method having an arbitration packet protocol |
US8164375B2 (en) | 2004-04-05 | 2012-04-24 | Round Rock Research, Llc | Delay line synchronizer apparatus and method |
US7774559B2 (en) | 2004-05-28 | 2010-08-10 | Micron Technology, Inc. | Method and system for terminating write commands in a hub-based memory system |
EP1769361A4 (en) * | 2004-05-28 | 2009-12-02 | Micron Technology Inc | Method and system for terminating write commands in a hub-based memory system |
EP1769361A2 (en) * | 2004-05-28 | 2007-04-04 | Micron Technology, Inc. | Method and system for terminating write commands in a hub-based memory system |
US7765368B2 (en) | 2004-07-30 | 2010-07-27 | International Business Machines Corporation | System, method and storage medium for providing a serialized memory interface with a bus repeater |
EP1628225A3 (en) * | 2004-07-30 | 2008-11-05 | International Business Machines Corporation | Bus speed multiplier in a memory subsystem |
EP1628225A2 (en) * | 2004-07-30 | 2006-02-22 | International Business Machines Corporation | Bus speed multiplier in a memory subsystem |
US7844771B2 (en) | 2004-10-29 | 2010-11-30 | International Business Machines Corporation | System, method and storage medium for a memory subsystem command interface |
US8589769B2 (en) | 2004-10-29 | 2013-11-19 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
US8140942B2 (en) | 2004-10-29 | 2012-03-20 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
US8495328B2 (en) | 2005-11-28 | 2013-07-23 | International Business Machines Corporation | Providing frame start indication in a memory system having indeterminate read data latency |
US8151042B2 (en) | 2005-11-28 | 2012-04-03 | International Business Machines Corporation | Method and system for providing identification tags in a memory system having indeterminate data response times |
US8145868B2 (en) | 2005-11-28 | 2012-03-27 | International Business Machines Corporation | Method and system for providing frame start indication in a memory system having indeterminate read data latency |
US8327105B2 (en) | 2005-11-28 | 2012-12-04 | International Business Machines Corporation | Providing frame start indication in a memory system having indeterminate read data latency |
US7685392B2 (en) | 2005-11-28 | 2010-03-23 | International Business Machines Corporation | Providing indeterminate read data latency in a memory system |
DE102006006571A1 (en) * | 2006-02-13 | 2007-08-16 | Infineon Technologies Ag | Semiconductor arrangement and method for operating a semiconductor device |
US7669086B2 (en) | 2006-08-02 | 2010-02-23 | International Business Machines Corporation | Systems and methods for providing collision detection in a memory system |
US7870459B2 (en) | 2006-10-23 | 2011-01-11 | International Business Machines Corporation | High density high reliability memory module with power gating and a fault tolerant address and command bus |
US7721140B2 (en) | 2007-01-02 | 2010-05-18 | International Business Machines Corporation | Systems and methods for improving serviceability of a memory system |
Also Published As
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TWI223151B (en) | 2004-11-01 |
AU2001292776A1 (en) | 2002-03-26 |
US6625687B1 (en) | 2003-09-23 |
WO2002023353A3 (en) | 2003-07-31 |
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