WO2002013234A3 - Stabilized surface between a fluorosilicate glass dielectric and a liner/barrier layer - Google Patents

Stabilized surface between a fluorosilicate glass dielectric and a liner/barrier layer Download PDF

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Publication number
WO2002013234A3
WO2002013234A3 PCT/US2001/024177 US0124177W WO0213234A3 WO 2002013234 A3 WO2002013234 A3 WO 2002013234A3 US 0124177 W US0124177 W US 0124177W WO 0213234 A3 WO0213234 A3 WO 0213234A3
Authority
WO
WIPO (PCT)
Prior art keywords
plasma
nitrogen
hydrogen
fsg
layer
Prior art date
Application number
PCT/US2001/024177
Other languages
French (fr)
Other versions
WO2002013234A2 (en
Inventor
Farhad Moghadam
Dana Tribula
Saad Hichem M
Nety M Krishna
Nirmalya Maity
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of WO2002013234A2 publication Critical patent/WO2002013234A2/en
Publication of WO2002013234A3 publication Critical patent/WO2002013234A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

A method of stabilizing a fluorosilicate glass (FSG) (36, 40) used as an inter-level dielectric layer and having via or other holes (42, 44) formed therethrough for contacting an aluminium or copper metallization. The FSG layer including the hole is subjected first to a plasma of nitrogen and possibly hydrogen and then to an argon plasma. The nitrogen plasma creates a nitrogen-rich surface, which reacts with the after deposited titanium to form a thin stable TiN layer. The nitrogen plasma may be applied at relatively low power. The hydrogen plasma removes free fluorine in the FSG which can create problems with peeling. The hydrogen/nitrogen may be supplied in the form of forming gas containing less than 7 % hydrogen. The subsequent argon plasma cleans the surface, including possibly removing a nitrided aluminium surface formed by the nitrogen plasma from an aluminium metallization. The process may also be applied to a copper dual-damascene metallization. After the two plasma treatments, a liner/barrier layer, preferably of Ti/TiN for Al and Ta/TaN for Cu, is coated on the walls of the hole and over the top of the FSG layer, and a metal is deposited in the hole to fill it.
PCT/US2001/024177 2000-08-04 2001-07-31 Stabilized surface between a fluorosilicate glass dielectric and a liner/barrier layer WO2002013234A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US63229200A 2000-08-04 2000-08-04
US09/632,292 2000-08-04

Publications (2)

Publication Number Publication Date
WO2002013234A2 WO2002013234A2 (en) 2002-02-14
WO2002013234A3 true WO2002013234A3 (en) 2002-08-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/024177 WO2002013234A2 (en) 2000-08-04 2001-07-31 Stabilized surface between a fluorosilicate glass dielectric and a liner/barrier layer

Country Status (1)

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WO (1) WO2002013234A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7049209B1 (en) 2005-04-01 2006-05-23 International Business Machines Corporation De-fluorination of wafer surface and related structure
CN104241120B (en) * 2013-06-13 2017-03-22 无锡华润上华科技有限公司 Method for preventing adhesive layer on edge of silicon wafer from falling off
US10312142B2 (en) 2016-11-28 2019-06-04 Northrop Grumman Systems Corporation Method of forming superconductor structures
US10276504B2 (en) 2017-05-17 2019-04-30 Northrop Grumman Systems Corporation Preclean and deposition methodology for superconductor interconnects

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213386A (en) * 1995-02-08 1996-08-20 Fujitsu Ltd Manufacture of semiconductor device
US5869149A (en) * 1997-06-30 1999-02-09 Lam Research Corporation Method for preparing nitrogen surface treated fluorine doped silicon dioxide films
US6008118A (en) * 1997-12-19 1999-12-28 United Microelectronics Corp. Method of fabricating a barrier layer
US6136680A (en) * 2000-01-21 2000-10-24 Taiwan Semiconductor Manufacturing Company Methods to improve copper-fluorinated silica glass interconnects
US6232217B1 (en) * 2000-06-05 2001-05-15 Chartered Semiconductor Manufacturing Ltd. Post treatment of via opening by N-containing plasma or H-containing plasma for elimination of fluorine species in the FSG near the surfaces of the via opening
US6252303B1 (en) * 1998-12-02 2001-06-26 Advanced Micro Devices, Inc. Intergration of low-K SiOF as inter-layer dielectric

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213386A (en) * 1995-02-08 1996-08-20 Fujitsu Ltd Manufacture of semiconductor device
US5869149A (en) * 1997-06-30 1999-02-09 Lam Research Corporation Method for preparing nitrogen surface treated fluorine doped silicon dioxide films
US6008118A (en) * 1997-12-19 1999-12-28 United Microelectronics Corp. Method of fabricating a barrier layer
US6252303B1 (en) * 1998-12-02 2001-06-26 Advanced Micro Devices, Inc. Intergration of low-K SiOF as inter-layer dielectric
US6136680A (en) * 2000-01-21 2000-10-24 Taiwan Semiconductor Manufacturing Company Methods to improve copper-fluorinated silica glass interconnects
US6232217B1 (en) * 2000-06-05 2001-05-15 Chartered Semiconductor Manufacturing Ltd. Post treatment of via opening by N-containing plasma or H-containing plasma for elimination of fluorine species in the FSG near the surfaces of the via opening

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 12 26 December 1996 (1996-12-26) *

Also Published As

Publication number Publication date
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