WO2002009181A1 - Vertically integrated chip on chip circuit stack - Google Patents

Vertically integrated chip on chip circuit stack Download PDF

Info

Publication number
WO2002009181A1
WO2002009181A1 PCT/US2001/023018 US0123018W WO0209181A1 WO 2002009181 A1 WO2002009181 A1 WO 2002009181A1 US 0123018 W US0123018 W US 0123018W WO 0209181 A1 WO0209181 A1 WO 0209181A1
Authority
WO
WIPO (PCT)
Prior art keywords
die
stack
integrated circuit
circuit die
spacer
Prior art date
Application number
PCT/US2001/023018
Other languages
French (fr)
Inventor
Alfons Vindasius
Marc E. Robinson
Original Assignee
Vertical Circuits, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vertical Circuits, Inc. filed Critical Vertical Circuits, Inc.
Priority to AU2001280684A priority Critical patent/AU2001280684A1/en
Publication of WO2002009181A1 publication Critical patent/WO2002009181A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

A vertically integrated chip on chip circuit stack provides a vertically integrated stack of die which includes two or more integrated circuit die, with the faces (circuitry) of the respective die surface up. The die are desirably of identical size, (length, and width). The die have electrical contacts at the edges of the top surface (face surface) and the bottom surface of each die is coated with an epoxy adhesive or glue where the adhesive is an electrical insulator. A spacer is between each integrated circuit die and sufficient thickness to allow write bond loops to be formed above such that the wires connected to the lower die do not touch the bottom surface of the die above. Electrically conducting wires are bonded to selected electrical contacts on each integrated circuit die. The conducting wires can be, for example, gold wires, or aluminium wires. The second end of the conducting wires are bonded to electrical conductors on a substrate which has electrical conductors. The electrical conductors on the top surface of the substrate are electrically connected to solder balls on a bottom surface of substrate. The stack and substrate can be molded in plastic, non conducting epoxy resin, other suitable molding compound or encapsulant.

Description

VERTICALLY INTEGRATED CHIP ON CHIP CIRCUIT STACK
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS
The present application is a continuation-in-part of co-pending applications Serial No. 08/917,447, filed 08/22/97 entitled "Conductive Epoxy Flip Chip on Chip", which is assigned to the same assignee of the present application and which is hereby incorporated by reference and applicant claims priority under 35 USC 120.
BACKGROUND OF THE INVENTION
The present invention relates to the stacking of die for forming vertically integrated stacks of die. One stacking approach is described in the above-identified cross-referenced application, which describes a flip chip on chip technology, in which the die are placed face to face on top of one another. Conductive epoxy is utilized in the flip chip on chip technology to make electrical interconnections between the die. While the flip chip on chip technology described in the above application provides various advantages and features, it would be desirable to provide an improved vertically integrated chip on chip stack, as will be described below.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved vertically integrated chip on chip circuit stack. In one embodiment, the present invention provides a vertically integrated stack of die which includes two or more integrated circuit die, with the faces (circuitry) of the respective die surface up. The die are desirably of identical size (length and width). The die have electrical contacts at the edges or perimeter of the top surface (face surface) and the bottom surface of each die is coated with an epoxy adhesive or glue where the adhesive is an electrical insulator. A spacer is between each integrated circuit die and of sufficient thickness to allow wire bond loops to be formed above such lower die that do not touch the bottom surface of the die above.
Electrically conducting wires are bonded to each electrical contact on each integrated circuit die. The conducting wires can be, for example, gold wires, or aluminum wires. The second end of the conducting wires are bonded to electrical conductors on a substrate which has electrical conductors. The electrical conductors on the top surface of the substrate are electrically connected to solder balls on a bottom surface of substrate. The stack and substrate can be molded in plastic, non conducting epoxy resin, other suitable molding compound or encapsulant.
Other objects, features and advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention, where like numerals identify like components, and, together with the following detailed description, serve to explain the principles of the invention:
Figs. 1 and 2 show a cross-section and side view of one embodiment of the present invention with a two high stack of die.
Figs. 3 and 4 show a cross-section and side view of one embodiment of the present invention with a two high stack of die with base plate (BGA).
Figs. 5 and 6 show a cross-section and side view of another embodiment of the present invention with a two high stack of die on BGA substrate.
Figs. 7 and 8 show a cross-section and side view of an embodiment of the present invention with a two high stack of die with base plate on lead frame.
Figs. 9 and 10 show a cross-section and side view of another embodiment of the present invention with a two high stack of die on lead frame.
Figs. 11 and 12 show a cross-section and side view of an embodiment of the present invention with a four high stack of die with base plate.
Figs. 13 and 14 show a cross-section and side view of an embodiment of the present invention with a four high stack of die with base plate/BGA.
Figs. 15 and 16 show a cross-section and side view of still another embodiment of the present invention with a four high stack of die on BGA substrate.
Figs. 17 and 18 show a cross-section and side view of an embodiment of the present invention with a four high stack of die on base plate on lead frame.
Figs. 19 and 20 show a cross-section and side view of still another embodiment of the present invention with a four high stack of die on lead frame.
DETAILED DESCRIPTION OF THE INVENTION
Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to those embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims.
The present invention provides a vertically integrated chip on chip circuit stack. In one embodiment, the present invention provides two (or more) integrated circuit die which are face to back with respect to one another. Wires are used for making vertical electrical interconnections, instead of conductive epoxy in the flip chip on chip technology. An insulator such as Parylene is not needed to protect the sides or the chips or die because the wires are rigid and do not touch the side of the die. A spacer is between the die to maintain spacing between the die so that the upper die does not touch the wires bonded to the lower die. The die are desirably of the same size.
Figs. 1 and 2 show a cross-section and side view of one embodiment of the present invention 12 with a two high stack of die. i Fig. 1, the cross-section view shows an active silicon die 14 above spacer 16, with a die adhesive/electrical insulator 18 between die 14 and spacer 16. A second die 20 is below spacer 16, with die adhesive 24 between second die 20 and spacer 16. A silicon base plate 26 is below second die 20, with die adhesive 28 between base plate 26 and second die 20.
In Figs. 1 and 2, electrical connections are made between base plate 26 and first die 14 via wire bonds 30. Electrical connections are made between second die 20 and base plate 26 via wire bonds 32.
As is apparent, die 14 and 20 in Figs. 1 and 2 are stacked face to back, and wires are used instead of conductive epoxy, as done in the above cross-referenced application, for the vertical electrical interconnection of the stacked die. The wires are rigid, and do not touch the sides of the die 14 and 20, so there is no need to use a material to insulate the sides of the die. The spacer 16 maintains the spacing between the die 14 and 20, so that the upper die 14 does not touch the wires bonded to the lower die 20. Desirably, die 14 and 20 are the same size. The bottom surface of each die 14 and 20 is coated with an die adhesive which is an electrical insulator. Similar aspects will become apparent in conjunction with the description of Figs. 3-20.
Figs. 3 and 4 show a cross-section and side view of one embodiment of the present invention 40 with a two high stack of die with base plate on a substrate (BGA- ball grid array). In Fig. 3, the cross-section view shows an active silicon die 14 above spacer 16, with a die adhesive/electrical insulator 18 between die 14 and spacer 16. A second die 20 is below spacer 16, with die adhesive 24 between second die 20 and spacer 16. A silicon base plate 26 is below second die 20, with die adhesive 28 between base plate 26 and second die 20. The base plate 26 is above a substrate 34, desirably a ball grid array (BGA) 34. A thin adhesive (not shown for clarity purposes)
would normally be placed between base plate 26 and substrate 35, as would be apparent
to one of ordinary skill. hi Figs. 3 and 4, electrical connections are made between base plate 26 and first die 14 via wire bonds 30. Electrical connections are made between second die 20 and base plate 26 via wire bonds 32. Electrical connections are made between base plate 26 and substrate 34 via wire bonds 38. The embodiment 40 shown in Figs. 3 and 4 is encapsulated by encapsulant 42.
Figs. 5 and 6 show a cross-section and side view of another embodiment of the present invention with a two high stack of die with substrate (BGA).
In Fig. 5, the cross-section view shows an active silicon die 14 above spacer 16, with a die adhesive/electrical insulator 18 between die 14 and spacer 16. A second die 20 is below spacer 16, with die adhesive 24 between second die 20 and spacer 16. A substrate 34, desirably a ball grid array (BGA), is below second die 20, with die adhesive 28 between base substrate 34 and second die 20. Encapsulant 42 encapsulates the circuit stack shown in Fig. 5.
In Figs. 5 and 6, electrical connections are made between substrate 34 and first die 14 via wire bonds 30. Electrical connections are made between second die 20 and substrate 34 via wire bonds 32.
Figs. 7 and 8 show a cross-section and side view of an embodiment of the present invention with a two high stack of die with base plate on lead frame.
In Fig. 7, the cross-section view shows an active silicon die 14 above spacer 16, with a die adhesive/electrical insulator 18 between die 14 and spacer 16. A second die 20 is below spacer 16, with die adhesive 24 between second die 20 and spacer 16. A silicon base plate 26 is below second die 20, with die adhesive 28 between base plate 26 and second die 20. The base plate 26 is above a lead-frame 50. An encapsulant 46 encapsulates the circuit stack shown in Fig. 7.
In Figs. 7 and 8, baseplate 26 is electrically interconnected to lead or terminal 54 via wire bonds 52. Electrical connections are made between baseplate 26 and first die 14 via wire bonds 30. Electrical connections are made between second die 20 and baseplate 26 via wire bonds 32.
Figs. 9 and 10 show a cross-section and side view of another embodiment of the present invention with a two high stack of die with base plate on lead frame.
In Fig. 9, the cross-section view shows an active silicon die 14 above spacer 16, with a die adhesive/electrical insulator 18 between die 14 and spacer 16. A second die 20 is below spacer 16, with die adhesive 24 between second die 20 and spacer 16. A lead-frame 50 is below second die 20, with die adhesive 28 between lead frame 50 and second die 20. An encapsulant 46 encapsulates the circuit stack shown in Fig. 9.
Electrical connections are made between lead 54 and first die 14 via wire bonds 30. Electrical connections are made between lead 54 and second die 20 via wire bonds 32.
Figs. 11 and 12 show a cross-section and side view of an embodiment of the present invention with a four high stack of die with base plate.
Figs. 11 and 12 show a cross-section and side view of one embodiment of the present invention with a four-high stack of die. i Fig. 11 , the cross-section view shows an active silicon die 14 above spacer 16, with a die adhesive/electrical insulator 18 between die 14 and spacer 16. A second die 20 is below spacer 16, with die adhesive 24 between second die 20 and spacer 16. A spacer 25 is below second die 20, with a die adhesive 28 between spacer 25 and second die 20. In Fig. 11, a third die 19 is below spacer 25, with die adhesive 33 between third die 19 and spacer 25. A spacer 27 is below third die 19, with die adhesive 35 between spacer 27 and die 19. In Fig. 11, a fourth die 21 is below spacer is below spacer 27, with die adhesive 37 between spacer 27 and die 21. A silicon base plate 26 is below die 21, with die adhesive 39 between base plate 26 and die 21. i Figs. 11 and 12, electrical connections are made between base plate 26 and die 14 via wire bonds 30. Electrical connections are made between second die 20 and base plate 26 via wire bonds 32. Similarly, electrical connections are made between third die 19 and base-plate 26 via wire bonds 43, and between fourth die 21 and baseplate 26 via wire bonds 45.
Figs. 13 and 14 show a cross-section and side view of an embodiment of the present invention with a four high stack of die with base plate/BGA.
Figs. 13 and 14 show a cross-section and side view of one embodiment of the present invention with a four-high stack of die with base-plate BGA. In Fig. 13, the cross-section view shows an active silicon die 14 above spacer 16, with a die adhesive/electrical insulator 18 between die 14 and spacer 16. A second die 20 is below spacer 16, with die adhesive 24 between second die 20 and' spacer 16. A spacer 25 is below second die 20, with a die adhesive 28 between spacer 25 and second die 20.
In Fig. 13, a third die 19 is below spacer 25, with die adhesive 33 between third die 19 and spacer 25. A spacer 27 is below third die 19, with die adhesive 35 between spacer 27 and die 19. In Fig. 13, a fourth die 21 is below spacer 27, with die adhesive 37 between spacer 27 and die 21. A silicon base plate 26 is below die 21, with die adhesive 39 between base plate 26 and die 21. A substrate, ball grid array (BGA) 34, is below base-plate 25. Encapsulant 42 encapsulates the circuit stack shown in Figs. 13 and 14.
In Figs. 13 and 14, electrical connections are made between base plate 26 and die 14 via wire bonds 30. Electrical connections are made between second die 20 and base plate 26 via wire bonds 32. Similarly, electrical connections are made between third die 19 and base-plate 26 via wire bonds 43, and between fourth die 21 and baseplate 26 via wire bonds 45. Wire bond 38 makes an electrical connection between base-plate 26 and substrate 34.
Figs. 15 and 16 show a cross-section and side view of still another embodiment of the present invention with a four high stack of die/BGA.
In Fig. 15, the cross-section view shows an active silicon die 14 above spacer 16, with a die adhesive/electrical insulator 18 between die 14 and spacer 16. A second die 20 is below spacer 16, with die adhesive 24 between second die 20 and spacer 16. A spacer 25 is below second die 20, with a die adhesive 28 between spacer 25 and second die 20. In Fig. 15, a third die 19 is below spacer 25, with die adhesive 33 between third die 19 and spacer 25. A spacer 27 is below third die 19, with die adhesive 35 between spacer 27 and die 19. h Fig. 15, a fourth die 21 is below spacer 27, with die adhesive 37 between spacer 27 and die 21. A substrate (ball grid array (BGA)) 34 is below die 21, with die adhesive 39 between substrate 34 and die 21. BGA encapsulant 42 encapsulates the circuit stack shown in Figs. 15 and 16.
In Figs. 15 and 16, electrical connections are made between substrate 34 and die 14 via wire bonds 30. Electrical connections are made between second die 20 and substrate 34 via wire bonds 32. Similarly, electrical connections are made between third die 19 and substrate 34 via wire bonds 43, and between fourth die 21 and substrate 34 via wire bonds 45.
Figs. 17 and 18 show a cross-section and side view of an embodiment of the present invention with a four high stack of die on lead frame. h Fig. 17, the cross-section view shows an active silicon die 14 above spacer 16, with a die adhesive/electrical insulator 18 between die 14 and spacer 16. A second die 20 is below spacer 16, with die adhesive 24 between second die 20 and spacer 16. A spacer 25 is below second die 20, with a die adhesive 28 between spacer 25 and second die 20. In Fig. 17, a third die 19 is below spacer 25, with die adhesive 33 between third die 19 and spacer 25. A spacer 27 is below third die 19, with die adhesive 35 between spacer 27 and die 19. In Fig. 17, a fourth die 21 is below spacer is below spacer 27, with die adhesive 37 between spacer 27 and die 21. A base-plate 26 is below die 21, with die adhesive 39 between base-plate 26 and die 21. A lead-frame50 is below base-plate 26. Encapsulant 46 encapsulates the circuit stack shown in Figs. 17 and 18.
In Figs. 17 and 18, electrical connections are made between base-plate 26 and die 14 via wire bonds 30. Electrical connections are made between second die 20 and base-plate 26 via wire bonds 32. Similarly, electrical connections are made between third die 19 and base-plate 26 via wire bonds 43, and between fourth die 21 and baseplate 26 via wire bonds 45. Base-plate 26 makes electrical interconnection with leads 54 of lead frame 50 via wire bonds 52. Figs. 19 and 20 show a cross-section and side view of still another embodiment of the present invention with a four high stack of die on lead frame.
In Fig. 19, the cross-section view shows an active silicon die 14 above spacer 16, with a die adhesive/electrical insulator 18 between die 14 and spacer 16. A second die 20 is below spacer 16, with die adhesive 24 between second die 20 and spacer 16. A spacer 25 is below second die 20, with a die adhesive 28 between spacer 25 and second die 20. In Fig. 19, a third die 19 is below spacer 25, with die adhesive 33 between third die 19 and spacer 25. A spacer 27 is below third die 19, with die adhesive 35 between spacer 27 and die 19. In Fig. 19, a fourth die 21 is below spacer is below spacer 27, with die adhesive 37 between spacer 27 and die 21. A lead-frame 50 is below die 21, with die adhesive 39 between lead-frame 50 and die 21. Encapsulant 46 encapsulates the circuit stack shown in Figs. 19 and 20. hi Figs. 19 and 20, electrical connections are made between leads 54 of lead frame 50 and die 14 via wire bonds 30. Electrical connections are made between lead 54 and die 20 via wire bonds 32. Similarly, electrical connections are made between third die 19 and lead 54 via wire bonds 43, and between fourth die 21 and lead 54 via wire bonds 45.
A vertically integrated chip on chip stack according to the present invention has been described in conjunction with Figs. 1-20. In one embodiment, the present
invention provides two (or more) integrated circuit die which are face to back with respect to one another. Wires are used for making vertical electrical interconnections, instead of conductive epoxy in the flip chip on chip technology. A material such as Parylene is not needed to protect the sides of the chips or die because the wires do not touch the side of the die. Spacers are between the die to maintain spacing between the die so that the upper die does not touch the wires bonded to the lower die. The die are desirably of the same size.
In one embodiment, the present invention provides a vertically integrated stack of die which includes two or more integrated circuit die, with the faces (circuitry)of the respective die surface up. The die are desirably of identical size (length, and width). The die have electrical contacts at the edges of the top surface (face surface) and the bottom surface of each die is coated with an epoxy adhesive or glue where the adhesive is an electrical insulator.
A spacer is between each integrated circuit die and of sufficient thickness to allow wire bond loops to be formed above such that the wire bonds connecting to the lower die do not touch the bottom surface of the die above.
Electrically conducting wires are bonded to each electrical contact on each integrated circuit die. The conducting wires can be, for example, gold wires, or aluminum wires. The second end of the conducting wires are bonded to electrical conductors on a substrate which has electrical conductors. The electrical conductors on the top surface of the substrate are electrically connected to solder balls on a bottom surface of substrate.
The stack and substrate can be molded in plastic, non-conducting epoxy resin, other suitable molding compound or encapsulant.
A leadframe can be used in place of the BGA substrate with the wires from each die in the stack bonded to the leads on the leadframe. The stack, leadframe, and wires, can be molded in plastic, non conducting epoxy resin, other suitable molding compound, or encapsulant.
A silicon baseplate can be used in place of the BGA substrate, with the wires from each die in the stack bonded to the electrically conducting leads on the baseplate. The stack and baseplate can be mounted in a ceramic cavity package, and the baseplate connections are wire bonded to appropriate electrical connection points of the ceramic cavity package.
The stack and baseplate can be mounted on a leadrame, with the wire bonds connecting the base plate to the leadframe. Plastic molding compound encapsulates the stack and leadframe.
The stack and baseplate can be mounted on BGA substrate, with the wire bonds connecting the baseplate to the BGA substrate and a plastic molding compound encapsulating the stack and leadframe.
The stack of integrated circuit die can include two, three, four or more integrated circuit die, and up to eight integrated circuit die. The stack can be of integrated circuit wafer segments, where each segment includes one or more integrated circuit die. The stack can include integrated circuit die or segments, where another die is flip chip bonded, face side down, to one or more of the die or segments in the stack. There is an ability to electrically program, select, or personalize, each layer in the stack through the use of one or more unique wire bond connections from that layer in the stack to the baseplate, BGA substrate, or leadframe.
The spacers can be made of silicon or of a thermoset plastic preform or of a thermoplastic preform.
The individual die or segment layers in the stacks can have their electrical connections rerouted (or not) from the original electrical connection points on the die to new connection points at the periphery of the top surface of each die or segment. The rerouting is accomplished by the use of a layer of polyimide, with holes made in the layer of polyimide, with a layer of thin film metal (usually gold or aluminum, but not restricted to such metal), the metal layer rerouting the original connection pads to new locations, and the option of a top polyimide layer to cover the metal layer, with access holes allowing connection to the metal layer. The stacked die can be "memory" die. The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and it should be understood that many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.

Claims

WHAT IS CLAIMED IS:
1. A vertically integrated stack of die comprising:
two or more integrated circuit die, face (circuitry) surface up; the die being of identical size (length, and width), the die having electrical contacts at the edges of the top surface (face surface), the bottom surface of each die coated with an epoxy adhesive or glue, the adhesive being an electrical insulator; a spacer between each integrated circuit die of sufficient thickness to allow wire bond loops to be formed above the lower die that do not touch the bottom surface of the die above, electrically conducting wires bonded to selected electrical contacts on each integrated circuit die, the second end of said conducting wires bonded to electrical conductors on a substrate having electrical conductors, the electrical conductors on the top surface of substrate electrically connected to solder balls or bumps on the bottom surface of the substrate, the stack and substrate molded in plastic, non conducting epoxy resin, other suitable molding compound, or encapsulant.
2. A stack of integrated circuit die as in Claim 1, with a leadframe in place of the BGA substrate and with the wires from each die in the stack bonded to the leads on the leadframe, the stack, leadframe, and wires, molded in plastic, non conducting epoxy resin, other suitable molding compound, or encapsulant.
3. A stack of integrated circuit die as in Claim 1, with a silicon baseplate in place of the BGA substrate with the wires from each die in the stack bonded to the electrically conducting leads on the baseplate.
4. A stack of integrated circuit die as in Claim 3, with the stack and the baseplate mounted in a ceramic cavity package and the baseplate connections wire bonded to appropriate electrical connection points of the ceramic cavity package.
5. A stack of integrated circuit die as described in Claim 3, with the stack and baseplate mounted on a leadrame, the wire bonds connecting the base plate to the leadframe and plastic molding compound encapsulating the stack and leadframe.
6 . A stack of integrated circuit die as in Claim 3, the stack and baseplate
mounted on BGA substrate wire bonds connecting the baseplate to the BGA substrate plastic molding compound encapsulating the stack and leadframe.
7. A stack of integrated circuit die as in Claims 1 through 6 including two integrated circuit die.
8. A stack of integrated circuit die as in Claims 1 through 6including three integrated circuit die.
9. A stack of integrated circuit die as in Claims 1 through 6 including four integrated circuit die.
10. A stack of integrated circuit die as in Claims 1 through 6 including between two and eight integrated circuit die.
11. A stack of integrated circuit die as in Claims 1 through 6, wherein the die include wafer segments, each segment including one or more integrated circuit die.
12. A stack of integrated circuit die or segments as in Claim 11, where another die is flip chip bonded, face side down, to one or more of the die or segments in the stack.
13. A stack of integrated circuit die as in Claims 1 through 12, including means to electrically program, select, or personalize, each layer in the stack through the use of one or more unique wire bond connections from that layer in the stack to the baseplate, BGA substrate, or leadframe.
14. The stack of integrated circuit die as in Claims 1 through 13 wherein each spacer is made of silicon.
15. The stack of integrated circuit die as in Claims 1 through 13 wherein each spacer is made of a thermoset plastic preform.
16. The stack of integrated circuit die as in Claims 1 through 13 wherein each spacer is made of a thermoplastic preform.
17. The stack of integrated circuit die as in Claims 1 through 13 wherein the individual die or segment layers in the stacks have had their electrical connections rerouted from the original electrical connection points on the die to new connection points at the periphery of the top surface of each die or segment.
18. The stack of integrated circuit die as in Claims 1 through 13 wherein the the rerouting is accomplished by the use of a layer of polyimide, holes made in the layer of polyimide, a layer of thin film metal, the metal layer rerouting the original connection pads to new locations, and the option of a top polyimide layer to cover the metal layer, with access holes allowing connection to the metal layer.
19. The stack of integrated circuit die as in Claims 1 through 13 wherein the stacked die are memory die.
PCT/US2001/023018 2000-07-20 2001-07-20 Vertically integrated chip on chip circuit stack WO2002009181A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001280684A AU2001280684A1 (en) 2000-07-20 2001-07-20 Vertically integrated chip on chip circuit stack

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62001100A 2000-07-20 2000-07-20
US09/620,011 2000-07-20

Publications (1)

Publication Number Publication Date
WO2002009181A1 true WO2002009181A1 (en) 2002-01-31

Family

ID=24484224

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/023018 WO2002009181A1 (en) 2000-07-20 2001-07-20 Vertically integrated chip on chip circuit stack

Country Status (2)

Country Link
AU (1) AU2001280684A1 (en)
WO (1) WO2002009181A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG130073A1 (en) * 2005-09-01 2007-03-20 Micron Technology Inc Stacked microelectronic devices and methods for manufacturing microelectronic devices
CN100411170C (en) * 2005-05-30 2008-08-13 矽品精密工业股份有限公司 Stack architecture of multiple chips
US7485969B2 (en) 2005-09-01 2009-02-03 Micron Technology, Inc. Stacked microelectronic devices and methods for manufacturing microelectronic devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291061A (en) * 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
US5323060A (en) * 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
US5442230A (en) * 1994-09-16 1995-08-15 National Semiconductor Corporation High density integrated circuit assembly combining leadframe leads with conductive traces
US5677569A (en) * 1994-10-27 1997-10-14 Samsung Electronics Co., Ltd. Semiconductor multi-package stack
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291061A (en) * 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
US5323060A (en) * 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
US5442230A (en) * 1994-09-16 1995-08-15 National Semiconductor Corporation High density integrated circuit assembly combining leadframe leads with conductive traces
US5677569A (en) * 1994-10-27 1997-10-14 Samsung Electronics Co., Ltd. Semiconductor multi-package stack
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100411170C (en) * 2005-05-30 2008-08-13 矽品精密工业股份有限公司 Stack architecture of multiple chips
SG130073A1 (en) * 2005-09-01 2007-03-20 Micron Technology Inc Stacked microelectronic devices and methods for manufacturing microelectronic devices
US7485969B2 (en) 2005-09-01 2009-02-03 Micron Technology, Inc. Stacked microelectronic devices and methods for manufacturing microelectronic devices
US7749808B2 (en) 2005-09-01 2010-07-06 Micron Technology, Inc. Stacked microelectronic devices and methods for manufacturing microelectronic devices

Also Published As

Publication number Publication date
AU2001280684A1 (en) 2002-02-05

Similar Documents

Publication Publication Date Title
US6426559B1 (en) Miniature 3D multi-chip module
US6222265B1 (en) Method of constructing stacked packages
US8143727B2 (en) Adhesive on wire stacked semiconductor package
US6759737B2 (en) Semiconductor package including stacked chips with aligned input/output pads
US6818980B1 (en) Stacked semiconductor package and method of manufacturing the same
US6492726B1 (en) Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
US8729690B2 (en) Assembly having stacked die mounted on substrate
US7282397B2 (en) Methods for designing bond pad rerouting elements for use in stacked semiconductor device assemblies and for assembling semiconductor devices
US7391105B2 (en) Unit semiconductor chip and multi chip package with center bonding pads and methods for manufacturing the same
US6560117B2 (en) Packaged microelectronic die assemblies and methods of manufacture
US7298032B2 (en) Semiconductor multi-chip package and fabrication method
TWI278947B (en) A multi-chip package, a semiconductor device used therein and manufacturing method thereof
US5757080A (en) Resin-sealed semiconductor device
US20020093087A1 (en) Semiconductor package with stacked dies
US20080026506A1 (en) Semiconductor multi-chip package and fabrication method
JP3494901B2 (en) Semiconductor integrated circuit device
KR100621547B1 (en) Multi-chip package
US20050156322A1 (en) Thin semiconductor package including stacked dies
JP3476383B2 (en) Semiconductor laminated package
JP2000049279A (en) Semiconductor device
US20080237831A1 (en) Multi-chip semiconductor package structure
WO2002009181A1 (en) Vertically integrated chip on chip circuit stack
JPS6370532A (en) Semiconductor device
KR100632476B1 (en) Multichip Packages and Semiconductor Chips Used in the Package
KR20010066269A (en) semiconductor package and metod for fabricating the same

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP