WO2002003436A1 - Thin compound semiconductor structure - Google Patents

Thin compound semiconductor structure Download PDF

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Publication number
WO2002003436A1
WO2002003436A1 PCT/US2001/016731 US0116731W WO0203436A1 WO 2002003436 A1 WO2002003436 A1 WO 2002003436A1 US 0116731 W US0116731 W US 0116731W WO 0203436 A1 WO0203436 A1 WO 0203436A1
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layer
monocrystalline
compound semiconductor
substrate
silicon
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PCT/US2001/016731
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French (fr)
Inventor
Douglas D. Fekete
William J. Ooms
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Motorola, Inc.
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Priority to AU2001274913A priority Critical patent/AU2001274913A1/en
Publication of WO2002003436A1 publication Critical patent/WO2002003436A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02469—Group 12/16 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02513—Microstructure
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3

Abstract

Semiconductor structures including compound semiconductor devices formed in semiconductor substrates and methods of producing the semiconductor devices and substrates that have improved thermal characteristics over conventional compound semiconductor devices and that may be formed substantially thinner than conventional semiconductor devices and substrates. The compound devices (1010) are formed in a layer of compound semiconductor material (1020) which overlies an accommodating layer (1030). The accommodating layer (1030) overlies a monocrystalline silicon semiconductor layer (1040). During the fabrication process, the silicon layer may be thinned by suitable methods, or removed entirely by chemical etching. When the silicon is removed by etching, the accommodating layer provides an etch-stop layer to protect the devices in the compound semiconductor layer.

Description

THIN COMPOUND SEMICONDUCTOR STRUCTURE
Background of the Invention
One problematic characteristic that exists in certain conventional compound semiconductor structures having semiconductor devices, such as GaAs semiconductor structures, is the poor thermal conductivity of compound semiconductor structures. For example, GaAs has a thermal conductivity of 0.46
I
1
Watts/centimeter*° Celsius s&s compared to Silicon, which has a thermal conductivity^'.of 1.5 atts/centimeter*° Celsius . '^Whe a GaAs semiconductor device is formed, and operates to generate heat, in a GaAs substrate, this poor thermal conductivity in GaAs creates a substantial, and undesirable, thermal gradient across the GaAs substrate .
Therefore, it would be desirable to provide compound semiconductor structures with characteristics that reduce the thermal gradient across the semiconductor structures.
Brief Description of the Drawings
FIGs . 1-3 illustrate schematically, in cross section, device structures that can be used in accordance with various embodiments of the invention.
FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer.
FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of illustrative semiconductor material manufactured in accordance with what is shown herein.
FIG. 6 is an x-ray diffraction taken on an illustrative semiconductor structure manufactured in accordance with what is shown herein.
FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer.
FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer.
FIG. 9 is a cross-sectional view of a conventional integrated circuit formed in a compound semiconductor substrate .
FIG. 10 is a cross-sectional view of a portion of an integrated circuit that includes a compound semiconductor layer, a template layer, an oxide layer and a monocrystalline semiconductor layer in accordance with the invention.
FIG. 11 is a cross-sectional view of a portion of an integrated circuit that includes a compound semiconductor layer, a template layer and an oxide layer.
FIG. 12 is a flow chart of an embodiment of a process according to the invention. Skilled artisans will appreciate that in many cases elements in certain FIGs . are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in certain FIGs . may be exaggerated relative to other elements to help to improve understanding of what is being shown.
Detailed Description of the Drawings
The present invention involves semiconductor structures of particular types. For convenience herein, these semiconductor structures are sometimes referred to as "composite semiconductor structures" or "composite integrated circuits" because they include two (or more) significantly different types of semiconductor devices in one integrated structure or circuit. For example, one of these two types of devices may be silicon-based devices such as CMOS devices, and the other of these two types of devices may be compound semiconductor devices such GaAs devices. Illustrative composite semiconductor structures and methods for making such structures are disclosed in Ramdani et al . U.S. patent application No. 09/502,023, filed February 10, 2000, which is hereby incorporated by reference herein in its entirety. Certain material from that reference is substantially repeated below to ensure that there is support herein for references to composite semiconductor structures and composite integrated circuits. FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 20 which may be relevant to or useful in connection with certain embodiments of the present invention. Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline compound semiconductor material. In this context, the term "monocrystalline" shall have the meaning commonly used within the semiconductor industry. The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
In accordance with one embodiment, structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24. Structure 20 may also include a template layer 30 between accommodating buffer layer 24 and compound semiconductor layer 26. As will be explained more fully below, template layer 30 helps to initiate the growth of compound semiconductor layer 26 on accommodating buffer layer 2 . Amorphous intermediate layer 28 helps to relieve the strain in accommodating buffer layer 24 and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer 24.
Substrate 22, in accordance with one embodiment, is a monocrystalline semiconductor wafer, preferably of large diameter. The wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA. Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Preferably substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry. Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate 22. In accordance with one embodiment, amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer 24 by the oxidation of substrate 22 during the growth of layer 24. Amorphous intermediate layer 28 serves to relieve strain that might otherwise occur in monocrystalline accommodating buffer layer 24 as a result of differences in the lattice constants of substrate 22 and buffer layer 24. As used herein, lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by amorphous intermediate layer 28, the strain may cause defects in the crystalline structure of accommodating buffer layer 24. Defects in the crystalline structure of accommodating buffer layer 24, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline compound semiconductor layer 26.
Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with underlying substrate 22 and with overlying compound semiconductor material 26. For example, the material could be an oxide or nitride having a lattice structure matched to substrate 22 and to the subsequently applied semiconductor material 26. Materials that are suitable for accommodating buffer layer 24 include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal haf ates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for accommodating buffer layer 24. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements.
Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide. The thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24. Typically, layer 28 has a thickness in the range of approximately 0.5-5 nm.
The compound semiconductor material of layer 26 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds) , mixed III- V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds. Examples include gallium arsenide (GaAs) , gallium indium arsenide (GalnAs) , gallium aluminum arsenide (GaAlAs) , indium phosphide (InP) , cadmium sulfide (CDs) , cadmium mercury telluride (CdHgTe) , zinc selenide (ZnSe) , zinc sulfur selenide (ZnSSe) , and the like. Suitable template 30 materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent compound semiconductor layer 26. Appropriate materials for template 30 are discussed below.
FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 in accordance with a further embodiment. Structure 40 is similar to the previously described semiconductor structure 20 except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline compound semiconductor material 26. Specifically, additional buffer layer 32 is positioned between the template layer 30 and the overlying layer 26 of compound semiconductor material. Additional buffer layer 32, formed of a semiconductor or compound semiconductor material, serves to provide a lattice compensation when the lattice constant of accommodating buffer layer 24 cannot be adequately matched to the overlying monocrystalline compound semiconductor material layer 26.
FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 34 in accordance with another exemplary embodiment of the invention. Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional semiconductor layer 38.
As explained in greater detail below, amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline semiconductor layer 26 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and semiconductor layer 38 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing--e.gr., compound semiconductor layer 26 formation.
The processes previously described above in connection with FIGS. 1 and 2 are adequate for growing monocrystalline compound semiconductor layers over a monocrystalline substrate. However, the process described in connection with FIG. 3, which includes transforming a monocrystalline accommodating buffer layer to an amorphous oxide layer, may be better for growing monocrystalline compound semiconductor layers because it allows any strain in layer 26 to relax.
Semiconductor layer 38 may include any of the materials described throughout this application in connection with either of compound semiconductor material layer 26 or additional buffer layer 32. For example, layer 38 may include monocrystalline Group IV or monocrystalline compound semiconductor materials.
In accordance with one embodiment of the present invention, semiconductor layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent semiconductor layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline semiconductor compound.
In accordance with another embodiment of the invention, semiconductor layer 38 comprises compound semiconductor material ( e . g. , a material discussed above in connection with compound semiconductor layer 26) that is thick enough to form devices within layer 38. In this case, a semiconductor structure in accordance with the present invention does not include compound semiconductor layer 26. In other words, the semiconductor structure in accordance with this embodiment only includes one compound semiconductor layer disposed above amorphous oxide layer 36.
The layer formed on substrate 22, whether it includes only accommodating buffer layer 24, accommodating buffer layer 24 with amorphous intermediate or interface layer 28, or an amorphous layer such as layer 36 formed by annealing layers 24 and 28 as described above in connection with FIG. 3, may be referred to generically as an "accommodating layer. "
The following non-limiting, illustrative examples illustrate various combinations of materials useful in structures 20, 40 and 34 in accordance with various alternative embodiments. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples. Example 1
In accordance with one embodiment, monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction. Silicon substrate 22 can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm. In accordance with this embodiment, accommodating buffer layer 24 is a monocrystalline layer of Sr2Baι-zTi03 where z ranges from 0 to 1 and amorphous intermediate layer 28 is a layer of silicon oxide (SiOx) formed at the interface between silicon substrate 22 and accommodating buffer layer 24. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26. Accommodating buffer layer 24 can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer 24 thick enough to isolate compound semiconductor layer 26 from substrate 22 to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed. The amorphous intermediate layer 28 of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm. In accordance with this embodiment, compound semiconductor material layer 26 is a layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers (μm) and preferably a thickness of about 0.5 μm to 10 μm. The thickness generally depends on the application for which the layer is being prepared.
To facilitate the epitaxial growth of the gallium arsenide or aluminum gallium arsenide on the monocrystalline oxide, a template layer 30 is formed by capping the oxide layer. Template layer 30 is preferably 1-10 monolayers of Ti-As, Sr-O-As, Sr-Ga-O, or Sr-Al-O. By way of a preferred example, 1-2 monolayers 30 of Ti-As or Sr-Ga-0 have been shown to successfully grow GaAs layers 26.
Example 2
In accordance with a further embodiment, monocrystalline substrate 22 is a silicon substrate as described above. Accommodating buffer layer 24 is a monocrystalline oxide of strontium or barium zirconate or hafnate in a cubic or orthorhombic phase with an amorphous intermediate layer 28 of silicon oxide formed at the interface between silicon substrate 22 and accommodating buffer layer 24. Accommodating buffer layer 24 can have a thickness of about 2-100 nm and preferably has a thickness of at least 5 nm to ensure adequate crystalline and surface quality and is formed of a monocrystalline SrZr03, BaZr03, SrHf03, BaSn03 or BaHf03. For example, a monocrystalline oxide layer of BaZr03 can grow at a temperature of about 700 degrees C. The lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate 22 silicon lattice structure.
An accommodating buffer layer 24 formed of these zirconate or hafnate materials is suitable for the growth of compound semiconductor materials 26 in the indium phosphide (InP) system. The compound semiconductor material 26 can be, for example, indium phosphide (InP) , indium gallium arsenide (InGaAs) , aluminum indium arsenide, (AlInAs) , or aluminum gallium indium arsenic phosphide (AlGalnAsP) , having a thickness of about 1.0 nm to 10 μm. A suitable template 30 for this structure is 1-10 monolayers of zirconium-arsenic (Zr-As) , zirconium-phosphorus (Zr-P) , hafnium-arsenic (Hf-As) , hafnium-phosphorus (Hf-P) , strontium-oxygen-arsenic (Sr-O-As) , strontium-oxygen- phosphorus (Sr-O-P) , barium-oxygen-arsenic (Ba-O-As) , indium-strontium-oxygen (In-Sr-0) , or barium-oxygen- phosphorus (Ba-O-P) , and preferably 1-2 monolayers of one of these materials. By way of an example, for a barium zirconate accommodating buffer layer 24, the surface is terminated with 1-2 monolayers of zirconium followed by deposition of 1-2 monolayers of arsenic to form a Zr-As template 30. A monocrystalline layer 26 of the compound semiconductor material from the indium phosphide system is then grown on template layer 30. The resulting lattice structure of the compound semiconductor material 26 exhibits a 45 degree rotation with respect to the accommodating buffer layer 24 lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%.
Example 3
In accordance with a further embodiment, a structure is provided that is suitable for the growth of an epitaxial film of a II-VI material overlying a silicon substrate 22. The substrate 22 is preferably a silicon wafer as described above. A suitable accommodating buffer layer 24 material is SrxBaι-xTi03, where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm. The II-VI compound semiconductor material 26 can be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe) . A suitable template 30 for this material system includes 1-10 monolayers of zinc-oxygen (Zn-0) followed by 1-2 monolayers of an excess of zinc followed by the selenidation of zinc on the surface. Alternatively, a template 30 can be, for example, 1-10 monolayers of strontium-sulfur (Sr-S) followed by the ZnSeS.
Example 4
This embodiment of the invention is an example of structure 40 illustrated in FIG. 2. Substrate 22, monocrystalline oxide layer 24, and monocrystalline compound semiconductor material layer 26 can be similar to those described in example 1. In addition, an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline semiconductor material. Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs) , an indium gallium phosphide (InGaP) , an aluminum gallium phosphide (AlGaP) , an indium gallium arsenide (InGaAs) , an aluminum indium phosphide (AllnP) , a gallium arsenide phosphide (GaAsP) , or an indium gallium phosphide (InGaP) strain compensated superlattice. In accordance with one aspect of this embodiment, buffer layer 32 includes a GaAsxPι-x superlattice, wherein the value of x ranges from 0 to 1. In accordance with another aspect, buffer layer 32 includes an InyGaι-yP superlattice, wherein the value of y ranges from 0 to 1. By varying the value of x or y, as the case may be, the lattice constant is varied from bottom to top across the superlattice to create a match between lattice constants of the underlying oxide and the overlying compound semiconductor material . The compositions of other materials, such as those listed above, may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner. The superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm. The template for this structure can be the same of that described in example 1. Alternatively, buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm. In using a germanium buffer layer, a template layer of either germanium-strontium (Ge-Sr) or germanium-titanium (Ge-Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline compound semiconductor material layer. The formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium. The monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond.
Example 5
This example also illustrates materials useful in a structure 40 as illustrated in FIG. 2. Substrate material 22, accommodating buffer layer 24, monocrystalline compound semiconductor material layer 26 and template layer 30 can be the same as those described above in example 2. In addition, a buffer layer 32 is inserted between accommodating buffer layer 24 and overlying monocrystalline compound semiconductor material layer 26. Buffer layer 32, a further monocrystalline semiconductor material, can be, for example, a graded layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide (InAlAs) . In accordance with one aspect of this embodiment, buffer layer 32 includes InGaAs, in which the indium composition varies from 0 to about 47%. Buffer layer 32 preferably has a thickness of about 10-30 nm.
Varying the composition of buffer layer 32 from GaAs to InGaAs serves to provide a lattice match between the underlying monocrystalline oxide material 24 and the overlying layer 26 of monocrystalline compound semiconductor material. Such a buffer layer 32 is especially advantageous if there is a lattice mismatch between accommodating buffer layer 24 and monocrystalline compound semiconductor material layer 26.
Example 6
This example provides exemplary materials useful in structure 34, as illustrated in FIG. 3. Substrate material 22, template layer 30, and monocrystalling compound semiconductor material layer 26 may be the same as those described above in connection with example 1.
Amorphous layer 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above) . For example, amorphous layer 36 may include a combination of SiOx and SrzBal-z Ti03 (where z ranges from 0 to 1) ,which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36.
The thickness of amorphous layer 36 may vary from application to application and may depend on such factors as desired insulating properties of layer 36, type of semiconductor material comprising layer 26, and the like. In accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5-6 nm.
Layer 38 comprises a monocrystalline compound semiconductor material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24. In accordance with one embodiment of the invention, layer 38 includes the same materials as those comprising layer 26. For example, if layer 26 includes GaAs, layer 38 also includes GaAs. However, in accordance with other embodiments of the present invention, layer 38 may include materials different from those used to form layer 26. In accordance with one exemplary embodiment of the invention, layer 38 is about 1 monolayer to about 100 nm thick.
Referring again to FIGS. 1-3, substrate 22 is a monocrystalline substrate such as a monocrystalline silicon substrate. The crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation. In similar manner, accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation. The lattice constants of accommodating buffer layer 24 and monocrystalline substrate 22 must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved. In this context the terms "substantially equal" and "substantially matched" mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.
FIG. 3 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal. Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved. In accordance with one embodiment, substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate . Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material 24 by 45° with respect to the crystal orientation of the silicon substrate wafer 22. The inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer 24 that might result from any mismatch in the lattice constants of the host silicon wafer 22 and the grown titanate layer 24. As a result, a high quality, thick, monocrystalline titanate layer 24 is achievable.
Still referring to FIGS. 1-3, layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation. In accordance with one embodiment of the invention, the lattice constant of layer 26 differs from the lattice constant of substrate 22. To achieve high crystalline quality in this epitaxially grown monocrystalline layer, accommodating buffer layer 24 must be of high crystalline quality. In addition, in order to achieve high crystalline quality in layer 26, substantial matching between the crystal lattice constant of the host crystal, in this case, monocrystalline accommodating buffer layer 24, and grown crystal 26 is desired. With properly selected materials this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of grown crystal 26 with respect to the orientation of host crystal 24. If grown crystal 26 is gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and accommodating buffer layer 24 is monocrystalline SrxBax_xTi03, substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of grown layer 26 is rotated by 45° with respect to the orientation of the host monocrystalline oxide 24. Similarly, if host material 24 is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and compound semiconductor layer 26 is indium phosphide or gallium indium arsenide or aluminum indium arsenide, substantial matching of crystal lattice constants can be achieved by rotating the orientation of grown crystal layer 26 by 45° with respect to host oxide crystal 24. In some instances, a crystalline semiconductor buffer layer 32 between host oxide 24 and grown compound semiconductor layer 26 can be used to reduce strain in grown monocrystalline compound semiconductor layer 26 that might result from small differences in lattice constants. Better crystalline quality in grown monocrystalline compound semiconductor layer 26 can thereby be achieved.
The following example illustrates a process, in accordance with one embodiment, for fabricating a semiconductor structure such as the structures depicted in FIGS. 1-3. The process starts by providing a monocrystalline semiconductor substrate 22 comprising silicon or germanium. In accordance with a preferred embodiment, semiconductor substrate 22 is a silicon wafer having a (100) orientation. Substrate 22 is preferably oriented on axis or, at most, about 0.5° off axis. At least a portion of semiconductor substrate 22 has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term "bare" in this context means that the surface in the portion of substrate 22 has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term "bare" is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process. In order to epitaxially grow a monocrystalline oxide layer 24 overlying monocrystalline substrate 22, the native oxide layer must first be removed to expose the crystalline structure of underlying substrate 22. The following process is preferably carried out by molecular beam epitaxy (MBE) , although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus. In the case where strontium is used, the substrate 22 is then heated to a temperature of about 750° C to cause the strontium to react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon. The ordered 2x1 structure forms a template for the ordered growth of an overlying layer 24 of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer 24.
In accordance with an alternate embodiment, the native silicon oxide can be converted and the surface of substrate 22 can be prepared for the growth of a monocrystalline oxide layer 24 by depositing an alkali earth metal oxide, such as strontium oxide or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750° C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate 22 surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer 24.
Following the removal of the silicon oxide from the surface of substrate 22, the substrate is cooled to a temperature in the range of about 200-800° C and a layer 24 of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer 28 at the interface between underlying substrate 22 and the growing strontium titanate layer 24. The growth of silicon oxide layer 28 results from the diffusion of oxygen through the growing strontium titanate layer 24 to the interface where the oxygen reacts with silicon at the surface of underlying substrate 22. The strontium titanate grows as an ordered monocrystal 24 with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of underlying substrate 22. Strain that otherwise might exist in strontium titanate layer 24 because of the small mismatch in lattice constant between silicon substrate 22 and the growing crystal 24 is relieved in amorphous silicon oxide intermediate layer 28.
After strontium titanate layer 24 has been grown to the desired thickness, the monocrystalline strontium titanate is capped by a template layer 30 that is conducive to the subsequent growth of an epitaxial layer of a desired compound semiconductor material 26.
For the subsequent growth of a layer 26 of gallium arsenide, the MBE growth of strontium titanate monocrystalline layer 24 can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen. Following the formation of this capping layer, . arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O-As. Any of these form an appropriate template 30 for deposition and formation of a gallium arsenide monocrystalline layer 26. Following the formation of template 30, gallium is subsequently introduced to the reaction with the arsenic and gallium arsenide 26 forms. Alternatively, gallium can be deposited on the capping layer to form a Sr-O-Ga bond, and arsenic is subsequently introduced with the gallium to form the GaAs.
FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the present invention. Single crystal SrTi03 accommodating buffer layer 24 was grown epitaxially on silicon substrate 22. During this growth process, amorphous interfacial layer 28 is formed which relieves strain due to lattice mismatch. GaAs compound semiconductor layer 26 was then grown epitaxially using template layer 30.
FIG. 6 illustrates an x-ray diffraction spectrum taken on structure including GaAs compound semiconductor layer 26 grown on silicon substrate 22 using accommodating buffer layer 24. The peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated.
The structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer 32 deposition step. Buffer layer 32 is formed overlying template layer 30 before the deposition of monocrystalline compound semiconductor layer 26. If buffer layer 32 is a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template 30 described above. If instead buffer layer 32 is a layer of germanium, the process above is modified to cap strontium titanate monocrystalline layer 24 with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or titanium. The germanium buffer layer 32 can then be deposited directly on this template 30.
Structure 34, illustrated in FIG. 3, may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above. The accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36. Layer 26 is then subsequently grown over layer 38. Alternatively, the anneal process may be carried out subsequent to growth of layer 26.
In accordance with one aspect of this embodiment, layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and semiconductor layer 38 to a rapid thermal anneal process with a peak temperature of about 700° C to about 1000°G and a process time of about 1 to about 10 minutes. However, other suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention. For example, laser annealing or "conventional" thermal annealing processes (in the proper environment) may be used to form layer 36. When conventional thermal annealing is employed to form layer 36, an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process. For example, when layer 38 includes GaAs, the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 38.
As noted above, layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26. Accordingly, any deposition or growth methods described in connection with either layer 32 or 26, may be employed to deposit layer 38. FIG. 7 is a high resolution Transmission Electron Micrograph (TEM) • of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3. In Accordance with this embodiment, a single crystal SrTi03 accommodating buffer layer was grown epitaxially on silicon substrate 22. During this growth process, an amorphous interfacial layer forms as described above. Next, GaAs layer 38 is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 36.
FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including GaAs compound semiconductor layer 38 and amorphous oxide layer 36 formed on silicon substrate 22. The peaks in • the spectrum indicate that GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amorphous.
The process described above illustrates a process for forming a semiconductor structure including a silicon substrate 22, an overlying oxide layer, and a monocrystalline gallium arsenide compound semiconductor layer 26 by the process of molecular beam epitaxy. The process can also be carried out by the process of chemical vapor deposition (CVD) , metal organic chemical vapor deposition (MOCVD) , migration enhanced epitaxy (MEE) , atomic layer epitaxy (ALE) , physical vapor deposition (PVD) , chemical solution deposition (CSD) , pulsed laser deposition (PLD) , or the like. Further, by a similar process, other monocrystalline accommodating buffer layers 24 such as alkaline earth metal titanates, zirconates, haf ates, tantalates, vanadates, ruthenates, and niobates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown. Further, by a similar process such as MBE, other III-V and II-VI monocrystalline compound semiconductor layers 26 can be deposited overlying monocrystalline oxide accommodating buffer layer 24.
Each of the variations of compound semiconductor materials 26 and monocrystalline oxide accommodating buffer layer 24 uses an appropriate template 30 for initiating the growth of the compound semiconductor layer. For example, if accommodating buffer layer 24 is an alkaline earth metal zirconate, the oxide can be capped by a thin layer of zirconium. The deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively. Similarly, if monocrystalline oxide accommodating buffer layer 24 is an alkaline earth metal hafnate, the oxide layer can be capped by a thin layer of hafnium. The deposition of hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer 26, respectively. In a similar manner, strontium titanate 24 can be capped with a layer of strontium or strontium and oxygen, and barium titanate 24 can be capped with a layer of barium or barium and oxygen. Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template 30 for the deposition of a compound semiconductor material layer 26 comprising indium gallium arsenide, indium aluminum arsenide, or indium phosphide.
A particularly preferred embodiment of the invention relates to heat-producing semiconductor devices. This embodiment, shown in FIGs. 9-12, is a semiconductor structure or integrated circuit formed having (a) at least one non-compound semiconductor portion, such as a monocrystalline silicon portion, as in FIGs. l-3b, (b) an accommodating layer, such as an oxide layer -- e.g., strontium titanate -- overlying the silicon portion and (c) one or more compound semiconductor portions, such as GaAs, and then thinned to an advantageous thickness. In one particular embodiment, the monocrystalline silicon portion is substantially entirely removed during the thinning process. The thinning process alleviates certain problems that exist with reducing thermal stress in particular compound semiconductor structures, as will be explained.
FIG. 9 shows a conventional compound semiconductor structure 900 including a compound semiconductor device 910, such as a GaAs power FET (Field Effect Transistor) , formed in a substantially wholly GaAs substrate 920 (the broken lines on the sides of substrate 920 (and layer 1020 in FIG. 10) indicate that the layers in FIG. 9 are not drawn to scale) .
Typically, when GaAs substrate 920 is formed, it is between about 0.5 and 1.0 millimeters thick. This thickness, however, is not viable for providing a substrate for conventional heat-producing semiconductor devices because of the poor thermal conductivity of GaAs. Generally, therefore, GaAs substrate 920 is thinned to between about 12 μm and about 125 μm by mechanical grinding or other suitable thinning process to allow for the placement of a heat sink 930 proximal to device 910. Commonly available thinning processes do not permit thinning of substrate 920 to less than between 12 μm and 125 μm because substrate 920 is brittle and tends to break under the stress of continued mechanical grinding. Other thinning processes, such as chemical etching, which do not abrade substrate 910, are not reliable for thinning any conventional single-crystal substrate to a desired thickness because there is no dependable, repeatable way to stop the chemical etching at any particular point.
Heat sink 930 reduces the thermal gradient across substrate 920 by removing the heat created by operation of the semiconductor device. However, because heat sink 930 is between about 12 μm and 125 μm distant from device 910, the relatively poor thermal characteristics of GaAs substrate 920 reduce the ability of heat sink 930 to efficiently drain away the heat from device 910.
From the foregoing, it is clear that it would be desirable to improve the thermal gradient of the substrate of a GaAs, or other compound semiconductor, device . One desirable way to improve the thermal gradient of the substrate of a GaAs device is to thin the substrate in which a GaAs device was formed without breaking the substrate .
FIG. 10 shows a preferred embodiment of a semiconductor structure 1000 according to the invention which improves the thermal properties of a GaAs semiconductor device 1010 in a GaAs layer 1020 by forming layer 1020 overlying a strontium titanate accommodating buffer layer 1030 (though there may be a template layer 1060 formed between layer 1020 and accommodating buffer layer 1030 as will be explained) which, in turn, overlies a silicon substrate 1040. An amorphous portion of silicon substrate 1045 supports the overlying structure and reduces stress therein, as described with reference to FIGS. 1-8.
As mentioned above, silicon has a thermal conductivity of 1.5 Watts/centimeter*0 Celsius, which is substantially higher than GaAs. Thus, by forming device 1010 in a GaAs layer 1020 overlying accommodating buffer layer 1030 which overlies silicon substrate 1040 and thinning silicon substrate 1040 using conventional methods to between about 12 μ m and about 125 μm, and preferably to between about 50 μ m and 100 μm, the thermal conductivity between device 1010 and heat sink 1050 is improved by a factor of about 3 times. Substrate 1040 shown in FIG. 10 obtains this improvement even though the GaAs device is formed within a thin -- i.e., between about .1 μm and about 1 μm -- GaAs layer which overlies accommodating buffer layer 1030 (one example of the accommodating buffer layer material is strontium titanate) .
It should be noted that the structure in FIG. 10 may also include a template layer 1060, similar to template layer 30 shown in FIG. 1, and as described with respect to the structure in FIG. 1. The structure in FIG. 10 may also include an additional buffer layer (not shown) , similar to the buffer layer 32 shown in FIG. 2, and as described with respect to the structure FIG. 2. Each of these relatively thin layers do not substantially affect the thermal characteristics of the structure .
The following equations illustrate the advantage in thermal conductivity of using a silicon substrate for a GaAs device over using a GaAs substrate for a GaAs device (It should be noted that because accommodating buffer layer 1030 (typically strontium titanate) ' is only about 50 Angstroms thick, its effect on the total thermal conductivity is negligible) . Thermal resistance, RThermai, is given by the following equation.
Rτhermai = L (Length or thickness) /pτ(thermal conductivity for particular material) * (area) The thermal resistance for a conventional 50 μ m GaAs substrate is,
R-Thermai = 50 μm / ( 0 . 46 Watts /cm*° C ) * A
^Thermal = . 00011 CItl*° C/WattS * A
whereas, the thermal resistance of a GaAs device formed in a 1 μm GaAs substrate which overlies a thin oxide which, in turn, overlies a 49 μm silicon substrate, (thus a total thickness of 50 μ m) , is,
Rτhermai = 50 μm / ((1.5 Watts /cm*°C) * .98) +(0.46 Watts /cm*°C) * .02) * A
^Thermal = .000035 cm*° C/Watts * A
Thus, replacing the GaAs substrate with the silicon substrate improves the thermal resistance by a factor of .00011 /.000035 = 3.14 of the semiconductor structure. Therefore, a GaAs device formed in a silicon substrate obtains substantially more favorable thermal conductivity than a GaAs device formed in a pure GaAs substrate . It should be noted that the silicon in this illustration can be thinned using abrasive thinning processes such as mechanical grinding, electromechanical polishing, chemical- mechanical polishing or other suitable thinning process, to obtain the same 12 μ m to 125 μm thickness that is presently obtainable using substantially wholly GaAs structures .
In another alternative embodiment, the silicon substrate may be completely removed by a suitable process, such as chemical etching, such that the GaAs, or other compound semiconductor, device resides in a remaining substrate of between about 0.5 μ m and about 5.0 μm of compound semiconductor material. FIG. 11 shows a semiconductor structure 1100 including a GaAs device 1110 (or other suitable compound semiconductor device) formed in a GaAs layer 1120 (or other suitable compound semiconductor layer) overlying a strontium titanate accommodating buffer layer 1130 (or other suitable oxide layer) .
Accommodating buffer layer 1130 is originally formed overlying a silicon substrate in which an amorphous layer, similar to layer 1045 in FIG. 10, is formed. In this embodiment, however, etching may be used to completely remove either the entire silicon substrate or only the monocrystalline portion of the silicon substrate, up to, but not including the amorphous layer of the silicon substrate. While etching is typically not a dependable solution for use with a single-crystal substrate because it is a difficult process to control, if structure 1100 is formed first from GaAs layer 1120 overlying strontium titanate accommodating buffer layer 1130, which, in turn, overlies a silicon substrate (not shown) , similar to the structure 1000 shown in FIG. 10, the silicon substrate may be removed using etching as will be explained.
Similar to structure 1000 shown in FIG. 10, structure 1100 may first be formed overlying a silicon substrate. Then, because the strontium titanate layer has an etch-stopping property (strontium titanate can generally be thinned only by an ion-milling process) , the silicon may be etched away until the GaAs device resides in a substrate of less than 125 μ m, preferably between about 0.5 μm and about 5.0 μm of GaAs 1120 (and a very thin accommodating buffer layer 2030) and, most preferably between about 2.0 μm and about 4.0 μm, depending on the particular implementation. This process of selectively etching only the silicon is dependable and repeatable because the etching can be controlled to stop at the accommodating buffer layer 1130, thereby preserving the GaAs layer 1120. It follows that device 1110, which resides in GaAs layer 1120, is completely protected from the etching.
A structure formed according to this method substantially improves the thermal characteristics of the device. For example, a heat sink may be affixed within about 0.5 μm to 5.0 μm from the device instead of between 12 μm and 125 μm. Furthermore, the improved thermal characteristics allow more power to be used by device 1110 without burning the device out. In addition, the size and quality of the heat sink can be reduced because of the reduced proximity between device 1110 and heat sink 1150. It should be noted that the structure in FIG. 11 may also include a template layer 1160. The structure in FIG. 11 may also include an additional buffer layer (not shown) , similar to the buffer layer 32 shown in FIG. 2, and as described with respect to the structure FIG. 2. As mentioned above, each of these layers do not substantially effect the thermal characteristics of the structure.
The following equations illustrate the improved thermal characteristics of a GaAs device which resides in a 1 μm GaAs substrate. (Again, it should be noted that the relatively thin strontium titanate provides almost negligible effect on the thermal characteristics of the substrate . )
Rrermai = 1 μm / (0.46 Watts /cm*°C) * A Rτhermai = .0000022 cm*° C/Watts * A
Thus, a device formed in a 1 μm GaAs substrate improves the thermal resistance over a device formed in a 50 μm GaAs substrate by a factor of .00011 /.0000022 = 50.
FIG. 12 is a flow chart 1200 of a method of forming a semiconductor structure according to the invention. Box 1210 shows one embodiment of a method for fabricating a structure including the monocrystalline -- e.g., silicon -- substrate according to the invention. Box 1220 shows the formation of devices in the structure -- e.g., electrical or optical devices in the GaAs (electrical devices may also be implemented, if desired in the silicon substrate) . Box 1230 indicates that an adhesive element -- e.g., a flexible sticky tape -- may be adhered to the structure on its top side (where the devices are preferably formed) such that the individual die can be handled after they have been separated from the structure. Box 1240 indicates that the silicon substrate may then be partially removed from the structure -- i.e., by grinding or other suitable method -- or completely removed -- i.e., by chemical etching or other suitable method. Box 1250 indicates that the separating into individual die and packaging steps may be implemented - after the thinning.
In an alternative embodiment of the invention, the thinning step may be implemented after the individual die have been separated from the wafer. This embodiment is most suitable for thinning using chemical etching because chemical etching requires less stabilization of the individual die than other forms of thinning -- e.g., electro-mechanical polishing.
It should be noted that the invention is not limited to the above-described structure using GaAs, strontium titanate and silicon but rather may use other, different compound semiconductor structures, metallic oxides, and monocrystalline semiconductors, respectively, as described with respect to FIGs. 1-8.
Thus, it is seen that a compound semiconductor structure with improved thermal characteristics has been provided. In addition, a compound semiconductor structure that includes a compound semiconductor device may be produced, according to the invention, in a substantially thinner package than conventional compound semiconductor structures .
As used herein, the terms "comprises, " "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus .
One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.

Claims

WHAT IS CLAIMED IS:
1. A compound semiconductor structure comprising: a substrate having a thickness less than 12 μm, said substrate comprising: an accommodating layer; and a monocrystalline compound semiconductor layer of a first type formed overlying the accommodating layer; and a compound semiconductor device being formed at least partially within said monocrystalline compound semiconductor layer.
2. The compound semiconductor structure of claim 1, wherein the substrate further comprises a monocrystalline silicon layer, such that the substrate has a thickness between 12.0 μm and 125 μm.
3. The structure of claims 1 or 2 further comprising a buffer layer of monocrystalline semiconductor material formed between the accommodating layer and the compound semiconductor layer.
4. The structure of claim 3 wherein the buffer layer comprises a monocrystalline semiconductor material selected from the group consisting of: Germanium, a GaAsxPι-x superlattice, an InyGaι_yP superlattice, and an InGaAs superlattice.
5. The structure of claims 1 or 2 further comprising a template layer formed between the accommodating layer and the compound semiconductor layer.
6. The structure of claims 1 or 2 wherein said accommodating layer is characterized by an etch- stopping property.
7. The structure of claims 1 or 2 wherein the accommodating layer comprises a perovskite oxide.
8. The structure of claims 1 or 2 wherein the monocrystalline compound semiconductor material comprises a material selected from the group consisting of: GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe, AlInAs, CDS, CdHgTe, and ZnSeS .
9. A method for fabricating a semiconductor structure comprising: providing a monocrystalline silicon substrate; epitaxially growing a monocrystalline accommodating layer overlying the monocrystalline silicon substrate; forming an amorphous oxide layer between the monocrystalline silicon substrate and the monocrystalline accommodating layer; epitaxially growing a monocrystalline compound semiconductor layer overlying the monocrystalline accommodating layer; and thinning the silicon substrate.
10. The method of claim 9 wherein said thinning comprises at least one of: mechanical grinding, electromechanical polishing, and etching.
11. The method of claim 9 wherein said thinning comprises thinning said silicon wherein said structure comprises a thickness of between about 0.5 μ m and about 5.0 μm.
12. The method of claim 9 wherein said thinning comprises thinning said silicon wherein said structure comprises a thickness of between about 12.0 μm and about 125 μm.
13. The method of claim 9 wherein said epitaxially growing a monocrystalline accommodating layer comprises epitaxially growing a monocrystalline accommodating layer comprising etch-stopping properties, and wherein said thinning comprises: etching the substrate; and stopping the etching at the monocrystalline accommodating layer.
14. The method of claim 9 further comprising forming an optical device in the compound semiconductor layer, forming a logic device in the silicon substrate and coupling the optical device to the logic device.
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