WO2002003392A3 - Method and low-power circuits used to generate accurate drain voltage for flash memory core cells in read mode - Google Patents

Method and low-power circuits used to generate accurate drain voltage for flash memory core cells in read mode Download PDF

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Publication number
WO2002003392A3
WO2002003392A3 PCT/US2001/019344 US0119344W WO0203392A3 WO 2002003392 A3 WO2002003392 A3 WO 2002003392A3 US 0119344 W US0119344 W US 0119344W WO 0203392 A3 WO0203392 A3 WO 0203392A3
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
memory core
core cells
select gate
drain
Prior art date
Application number
PCT/US2001/019344
Other languages
French (fr)
Other versions
WO2002003392A2 (en
Inventor
Binh Q Le
Pau-Ling Chen
Michael A Vanbuskir
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to AU2001268495A priority Critical patent/AU2001268495A1/en
Publication of WO2002003392A2 publication Critical patent/WO2002003392A2/en
Publication of WO2002003392A3 publication Critical patent/WO2002003392A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells

Abstract

Control circuitry and a method for generating an accurate drain voltage for selected memory core cells in a semiconductor memory device during a Read mode of operation is provided. Select gate transistors (SG1 SGm) are provided which have their conduction path being coupled between a power supply voltage and a drain of one of the selected memory core cells. A differential amplifier circuit (202) is responsive to a bitline voltage corresponding to a drain voltage of the selected memory core cells and a reference voltage for generating a select gate voltage. The select gate voltage is decreased when the bitline voltage is higher than a target voltage and is increased when the bitline voltage is lower than the target voltage. A source follower circuit (204) is responsive to the select gate voltage for generating the bitline voltage which is maintained at the target voltage. The control gates of the select gate transistors are connected to receive the select gate voltage for maintaining the voltage at the drain of the selected memory core cells to be approximately constant.
PCT/US2001/019344 2000-07-03 2001-06-15 Method and low-power circuits used to generate accurate drain voltage for flash memory core cells in read mode WO2002003392A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001268495A AU2001268495A1 (en) 2000-07-03 2001-06-15 Method and low-power circuits used to generate accurate drain voltage for flash memory core cells in read mode

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/609,897 US6292399B1 (en) 2000-07-03 2000-07-03 Method and low-power circuits used to generate accurate drain voltage for flash memory core cells in read mode
US09/609,897 2000-07-03

Publications (2)

Publication Number Publication Date
WO2002003392A2 WO2002003392A2 (en) 2002-01-10
WO2002003392A3 true WO2002003392A3 (en) 2002-04-04

Family

ID=24442786

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/019344 WO2002003392A2 (en) 2000-07-03 2001-06-15 Method and low-power circuits used to generate accurate drain voltage for flash memory core cells in read mode

Country Status (4)

Country Link
US (1) US6292399B1 (en)
AU (1) AU2001268495A1 (en)
TW (1) TW512349B (en)
WO (1) WO2002003392A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW439293B (en) * 1999-03-18 2001-06-07 Toshiba Corp Nonvolatile semiconductor memory
US6870764B2 (en) * 2003-01-21 2005-03-22 Xicor Corporation Floating gate analog voltage feedback circuit
US7352618B2 (en) * 2004-12-15 2008-04-01 Samsung Electronics Co., Ltd. Multi-level cell memory device and associated read method
US7339846B2 (en) * 2006-07-14 2008-03-04 Macronix International Co., Ltd. Method and apparatus for reading data from nonvolatile memory
WO2008115155A1 (en) * 2007-03-19 2008-09-25 Vinko Kunc Method for regulating supply voltage
JP5325628B2 (en) * 2009-03-26 2013-10-23 ラピスセミコンダクタ株式会社 Semiconductor memory reference potential generation circuit
TWI512731B (en) * 2013-05-24 2015-12-11 Winbond Electronics Corp Readout circuit and memory device utilizing the same
KR102461866B1 (en) * 2018-03-27 2022-11-02 에스케이하이닉스 주식회사 Circuit for generating voltage

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5402370A (en) * 1993-09-10 1995-03-28 Intel Corporation Circuitry and method for selecting a drain programming voltage for a nonvolatile memory
US5495453A (en) * 1994-10-19 1996-02-27 Intel Corporation Low power voltage detector circuit including a flash memory cell

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69229995T2 (en) * 1992-06-30 2000-03-16 St Microelectronics Srl Voltage regulator for storage devices
DE69325278T2 (en) * 1993-12-31 1999-11-11 St Microelectronics Srl Non-volatile, electrically programmable semiconductor memory device with a voltage regulator
TW378321B (en) * 1996-02-29 2000-01-01 Sanyo Electric Co Semiconductor memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5402370A (en) * 1993-09-10 1995-03-28 Intel Corporation Circuitry and method for selecting a drain programming voltage for a nonvolatile memory
US5495453A (en) * 1994-10-19 1996-02-27 Intel Corporation Low power voltage detector circuit including a flash memory cell

Also Published As

Publication number Publication date
WO2002003392A2 (en) 2002-01-10
AU2001268495A1 (en) 2002-01-14
US6292399B1 (en) 2001-09-18
TW512349B (en) 2002-12-01

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