WO2002001639A3 - Substrate and module - Google Patents
Substrate and module Download PDFInfo
- Publication number
- WO2002001639A3 WO2002001639A3 PCT/DE2001/002373 DE0102373W WO0201639A3 WO 2002001639 A3 WO2002001639 A3 WO 2002001639A3 DE 0102373 W DE0102373 W DE 0102373W WO 0201639 A3 WO0201639 A3 WO 0201639A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- frequency
- substrate
- layer
- module
- low
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
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- H01L2223/66—High-frequency adaptations
- H01L2223/6688—Mixed frequency adaptations, i.e. for operation at different frequencies
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
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- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
Abstract
The invention relates to a substrate (S), comprising at least one first insulating layer (1), at least one high-frequency structural layer (4) that contains a high-frequency distributor network, at least one low-frequency structural layer (3) into which a voltage signal can be feed at the input side, the high-frequency structural layer (4) being separated from the low-frequency layer (3) by the insulating layer (1).
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10031658.1 | 2000-06-29 | ||
DE10031658A DE10031658A1 (en) | 2000-06-29 | 2000-06-29 | Microwave module comprising substrate with HF and LF layers forming distribution network structures, includes intervening insulating layer |
DE10041770.1 | 2000-08-25 | ||
DE10041770A DE10041770A1 (en) | 2000-08-25 | 2000-08-25 | Microwave module comprising substrate with HF and LF layers forming distribution network structures, includes intervening insulating layer |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002001639A2 WO2002001639A2 (en) | 2002-01-03 |
WO2002001639A3 true WO2002001639A3 (en) | 2002-06-27 |
Family
ID=26006226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2001/002373 WO2002001639A2 (en) | 2000-06-29 | 2001-06-27 | Substrate and module |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2002001639A2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3960277B2 (en) | 2002-10-23 | 2007-08-15 | 株式会社村田製作所 | High frequency module and communication device |
US6828514B2 (en) * | 2003-01-30 | 2004-12-07 | Endicott Interconnect Technologies, Inc. | High speed circuit board and method for fabrication |
CA2455024A1 (en) | 2003-01-30 | 2004-07-30 | Endicott Interconnect Technologies, Inc. | Stacked chip electronic package having laminate carrier and method of making same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5188280A (en) * | 1989-04-28 | 1993-02-23 | Hitachi Ltd. | Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals |
EP0961321A2 (en) * | 1998-05-29 | 1999-12-01 | Kyocera Corporation | High-frequency module |
US6008534A (en) * | 1998-01-14 | 1999-12-28 | Lsi Logic Corporation | Integrated circuit package having signal traces interposed between power and ground conductors in order to form stripline transmission lines |
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2001
- 2001-06-27 WO PCT/DE2001/002373 patent/WO2002001639A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5188280A (en) * | 1989-04-28 | 1993-02-23 | Hitachi Ltd. | Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals |
US6008534A (en) * | 1998-01-14 | 1999-12-28 | Lsi Logic Corporation | Integrated circuit package having signal traces interposed between power and ground conductors in order to form stripline transmission lines |
EP0961321A2 (en) * | 1998-05-29 | 1999-12-01 | Kyocera Corporation | High-frequency module |
Non-Patent Citations (2)
Title |
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BROWN R L ET AL: "THE INTEGRATION OF PASSIVE COMPONENTS INTO MCMS USING ADVANCED LOW-TEMPERATURE COFIRED CERAMICS", INTERNATIONAL JOURNAL OF MICROCIRCUITS AND ELECTRONIC PACKAGING, INTERNATIONAL MICROELECTRONICS & PACKAGING SOCIETY, US, VOL. 16, NR. 4, PAGE(S) 328-337, ISSN: 1063-1674, XP000408872 * |
DREVON ET AL: "Mixed LF/RF MCM", ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, 1997. PROCEEDINGS., 47TH SAN JOSE, CA, USA 18-21 MAY 1997, NEW YORK, NY, USA,IEEE, US, PAGE(S) 497-501, ISBN: 0-7803-3857-X, XP010234087 * |
Also Published As
Publication number | Publication date |
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WO2002001639A2 (en) | 2002-01-03 |
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