WO2002001345A3 - Method and apparatus for arbitration of concurrent processes in multiprocessor systems - Google Patents

Method and apparatus for arbitration of concurrent processes in multiprocessor systems Download PDF

Info

Publication number
WO2002001345A3
WO2002001345A3 PCT/EP2001/007193 EP0107193W WO0201345A3 WO 2002001345 A3 WO2002001345 A3 WO 2002001345A3 EP 0107193 W EP0107193 W EP 0107193W WO 0201345 A3 WO0201345 A3 WO 0201345A3
Authority
WO
WIPO (PCT)
Prior art keywords
arbitration
concurrent processes
risc
multiprocessor systems
dsp
Prior art date
Application number
PCT/EP2001/007193
Other languages
French (fr)
Other versions
WO2002001345A2 (en
Inventor
Valter Bella
Marco Gandini
Original Assignee
Telecom Italia Lab Spa
Valter Bella
Marco Gandini
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telecom Italia Lab Spa, Valter Bella, Marco Gandini filed Critical Telecom Italia Lab Spa
Publication of WO2002001345A2 publication Critical patent/WO2002001345A2/en
Publication of WO2002001345A3 publication Critical patent/WO2002001345A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

The method and the apparatus of this invention apply to a multiprocessor system in which a main processor RISC and a secondary processor DSP share the same external memory resources. The method permits arbitration of concurrent processes, particularly shared memory reading and writing operations, so that the DSP can adequately perform the assigned task without precluding the possibility of the RISC to reassume control of the system when required and thus preventing memory resource access redundancy.
PCT/EP2001/007193 2000-06-29 2001-06-25 Method and apparatus for arbitration of concurrent processes in multiprocessor systems WO2002001345A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT2000TO000643A IT1320466B1 (en) 2000-06-29 2000-06-29 PROCEDURE AND EQUIPMENT FOR THE ARBITRATION OF COMPETITIVE PROCESSES IN MULTIPROCESSOR SYSTEMS.
ITTO2000A000643 2000-06-29

Publications (2)

Publication Number Publication Date
WO2002001345A2 WO2002001345A2 (en) 2002-01-03
WO2002001345A3 true WO2002001345A3 (en) 2003-03-06

Family

ID=11457869

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/007193 WO2002001345A2 (en) 2000-06-29 2001-06-25 Method and apparatus for arbitration of concurrent processes in multiprocessor systems

Country Status (2)

Country Link
IT (1) IT1320466B1 (en)
WO (1) WO2002001345A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8705636B2 (en) 2009-06-04 2014-04-22 Telefonaktiebolaget L M Ericsson (Publ) Passive single-ended line test

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4679166A (en) * 1983-01-17 1987-07-07 Tandy Corporation Co-processor combination
US5392436A (en) * 1989-11-03 1995-02-21 Compaq Computer Corporation Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration
US5598575A (en) * 1993-11-01 1997-01-28 Ericsson Inc. Multiprocessor data memory sharing system in which access to the data memory is determined by the control processor's access to the program memory
US6078338A (en) * 1998-03-11 2000-06-20 Compaq Computer Corporation Accelerated graphics port programmable memory access arbiter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4679166A (en) * 1983-01-17 1987-07-07 Tandy Corporation Co-processor combination
US5392436A (en) * 1989-11-03 1995-02-21 Compaq Computer Corporation Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration
US5598575A (en) * 1993-11-01 1997-01-28 Ericsson Inc. Multiprocessor data memory sharing system in which access to the data memory is determined by the control processor's access to the program memory
US6078338A (en) * 1998-03-11 2000-06-20 Compaq Computer Corporation Accelerated graphics port programmable memory access arbiter

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"STATE MACHINE IMPLEMENTATION OF SHARED RAM ARBITER", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 31, no. 7, 1 December 1988 (1988-12-01), pages 83 - 85, XP000253951, ISSN: 0018-8689 *

Also Published As

Publication number Publication date
ITTO20000643A0 (en) 2000-06-29
ITTO20000643A1 (en) 2001-12-29
IT1320466B1 (en) 2003-11-26
WO2002001345A2 (en) 2002-01-03

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