WO2001099173A3 - Method of treating a substrate - Google Patents

Method of treating a substrate Download PDF

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Publication number
WO2001099173A3
WO2001099173A3 PCT/US2001/018733 US0118733W WO0199173A3 WO 2001099173 A3 WO2001099173 A3 WO 2001099173A3 US 0118733 W US0118733 W US 0118733W WO 0199173 A3 WO0199173 A3 WO 0199173A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
treating
metal
cleaning process
containing layer
Prior art date
Application number
PCT/US2001/018733
Other languages
French (fr)
Other versions
WO2001099173A2 (en
Inventor
Robin Cheung
Yezdi Dordi
Jennifer Tseng
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of WO2001099173A2 publication Critical patent/WO2001099173A2/en
Publication of WO2001099173A3 publication Critical patent/WO2001099173A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S134/00—Cleaning and liquid contact with solids
    • Y10S134/902—Semiconductor wafer

Abstract

A method of treating a substrate. The method comprises forming a metal-containing layer on at least a selected portion of the substrate during a substrate cleaning process.
PCT/US2001/018733 2000-06-22 2001-06-08 Method of treating a substrate WO2001099173A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/599,125 US6645550B1 (en) 2000-06-22 2000-06-22 Method of treating a substrate
US09/599,125 2000-06-22

Publications (2)

Publication Number Publication Date
WO2001099173A2 WO2001099173A2 (en) 2001-12-27
WO2001099173A3 true WO2001099173A3 (en) 2002-05-23

Family

ID=24398309

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/018733 WO2001099173A2 (en) 2000-06-22 2001-06-08 Method of treating a substrate

Country Status (2)

Country Link
US (2) US6645550B1 (en)
WO (1) WO2001099173A2 (en)

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