WO2001098830A3 - Modification of mask layout data to improve mask fidelity - Google Patents

Modification of mask layout data to improve mask fidelity Download PDF

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Publication number
WO2001098830A3
WO2001098830A3 PCT/US2001/012853 US0112853W WO0198830A3 WO 2001098830 A3 WO2001098830 A3 WO 2001098830A3 US 0112853 W US0112853 W US 0112853W WO 0198830 A3 WO0198830 A3 WO 0198830A3
Authority
WO
WIPO (PCT)
Prior art keywords
mask
layout data
fidelity
improve
modification
Prior art date
Application number
PCT/US2001/012853
Other languages
French (fr)
Other versions
WO2001098830A2 (en
Inventor
Ramkumar Subramanian
Khoi A Phan
Bhanwar Singh
Bharath Rangarajan
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to DE60101481T priority Critical patent/DE60101481T2/en
Priority to AU2001257130A priority patent/AU2001257130A1/en
Priority to EP01930611A priority patent/EP1290496B1/en
Publication of WO2001098830A2 publication Critical patent/WO2001098830A2/en
Publication of WO2001098830A3 publication Critical patent/WO2001098830A3/en

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]

Abstract

The present invention relates to a system and method of modifying (660) mask layout data (100) to improve the fidelity of mask manufacture. The system and method include determining (645, 650, 655) the difference between the mask layout design (100) and the mask features (20) as written, and generating sizing corrections (160). The sizing corrections (160) can be used to modify (660) the mask layout data (100), and/or stored in a database (170).
PCT/US2001/012853 2000-06-16 2001-04-19 Modification of mask layout data to improve mask fidelity WO2001098830A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE60101481T DE60101481T2 (en) 2000-06-16 2001-04-19 MODIFYING A MASK'S LAYOUT DATA TO IMPROVE THE GENERATED PATTERN
AU2001257130A AU2001257130A1 (en) 2000-06-16 2001-04-19 Modification of mask layout data to improve mask fidelity
EP01930611A EP1290496B1 (en) 2000-06-16 2001-04-19 Modification of mask layout data to improve mask fidelity

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/596,954 2000-06-16
US09/596,954 US6444373B1 (en) 2000-06-16 2000-06-16 Modification of mask layout data to improve mask fidelity

Publications (2)

Publication Number Publication Date
WO2001098830A2 WO2001098830A2 (en) 2001-12-27
WO2001098830A3 true WO2001098830A3 (en) 2002-07-25

Family

ID=24389425

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/012853 WO2001098830A2 (en) 2000-06-16 2001-04-19 Modification of mask layout data to improve mask fidelity

Country Status (5)

Country Link
US (2) US6444373B1 (en)
EP (1) EP1290496B1 (en)
AU (1) AU2001257130A1 (en)
DE (1) DE60101481T2 (en)
WO (1) WO2001098830A2 (en)

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JP4580529B2 (en) * 2000-09-26 2010-11-17 大日本印刷株式会社 Semiconductor circuit design pattern data correction method, photomask using corrected design pattern data, photomask inspection method, and photomask inspection pattern data preparation method
US6673638B1 (en) * 2001-11-14 2004-01-06 Kla-Tencor Corporation Method and apparatus for the production of process sensitive lithographic features
US6691052B1 (en) * 2002-01-30 2004-02-10 Kla-Tencor Corporation Apparatus and methods for generating an inspection reference pattern
US7302672B2 (en) * 2002-07-12 2007-11-27 Cadence Design Systems, Inc. Method and system for context-specific mask writing
EP1579274A4 (en) * 2002-07-12 2006-06-07 Cadence Design Systems Inc Method and system for context-specific mask inspection
WO2004008246A2 (en) * 2002-07-12 2004-01-22 Cadence Design Systems, Inc. Method and system for context-specific mask writing
US6792592B2 (en) * 2002-08-30 2004-09-14 Numerical Technologies, Inc. Considering mask writer properties during the optical proximity correction process
JP4040515B2 (en) 2003-03-26 2008-01-30 株式会社東芝 Mask setting, mask data creating method and pattern forming method
US6973637B2 (en) * 2003-05-12 2005-12-06 Agere Systems Inc. Process for the selective control of feature size in lithographic processing
US7318214B1 (en) 2003-06-19 2008-01-08 Invarium, Inc. System and method for reducing patterning variability in integrated circuit manufacturing through mask layout corrections
US7024638B2 (en) * 2003-07-14 2006-04-04 Cadence Design Systems, Inc. Method for creating patterns for producing integrated circuits
EP1644855A4 (en) * 2003-07-14 2007-08-01 Cadence Design Systems Inc Method for creating patterns for producing integrated circuits
US7261982B2 (en) * 2003-08-07 2007-08-28 Jds Uniphase Corporation Planar circuit optimization
US7266800B2 (en) * 2004-06-04 2007-09-04 Invarium, Inc. Method and system for designing manufacturable patterns that account for the pattern- and position-dependent nature of patterning processes
JP2008516272A (en) * 2004-10-05 2008-05-15 トッパン、フォウタマスクス、インク System and method for analyzing the shape of a photomask
US7588868B2 (en) * 2004-10-06 2009-09-15 Cadence Design Systems, Inc. Method and system for reducing the impact of across-wafer variations on critical dimension measurements
US7345738B2 (en) * 2004-12-03 2008-03-18 Asml Netherlands B.V. Certified cells and method of using certified cells for fabricating a device
US7465525B2 (en) * 2005-05-10 2008-12-16 Lam Research Corporation Reticle alignment and overlay for multiple reticle process
US7539969B2 (en) * 2005-05-10 2009-05-26 Lam Research Corporation Computer readable mask shrink control processor
US7392503B2 (en) * 2005-07-20 2008-06-24 Winbond Electronics Corp. Method of correcting mask pattern
US20070143234A1 (en) * 2005-12-16 2007-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method and system for intelligent model-based optical proximity correction (OPC)
US20090281778A1 (en) * 2006-12-21 2009-11-12 Nxp, B.V. Method and system for identifying weak points in an integrated circuit design
US20080241709A1 (en) * 2007-04-02 2008-10-02 Kent Nakagawa System And Method For analyzing photomask Geometries
JP5137444B2 (en) * 2007-04-04 2013-02-06 株式会社日立ハイテクノロジーズ OPC modeling construction method, information processing apparatus, and method for determining process conditions of semiconductor device
DE102009007770A1 (en) * 2009-02-05 2010-08-12 Carl Zeiss Sms Gmbh Corrective action determining method for electron beam lithographic mask writer, involves evaluating aerial image by test mask with respect to observation of tolerances based on test structures, and determining corrective action
US8103984B1 (en) * 2009-02-23 2012-01-24 Cadence Design Systems, Inc. System and method for compressed design phase contour data
US7944545B2 (en) * 2009-05-11 2011-05-17 International Business Machines Corporation High contrast lithographic masks
CN103309150B (en) * 2013-06-26 2015-06-17 上海华力微电子有限公司 Processing method for layout data
US9007719B1 (en) 2013-10-23 2015-04-14 Western Digital (Fremont), Llc Systems and methods for using double mask techniques to achieve very small features
WO2018125115A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Accounting for mask manufacturing infidelities in semiconductor devices
US11435660B2 (en) * 2017-11-22 2022-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Photomask and method of fabricating a photomask

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Also Published As

Publication number Publication date
AU2001257130A1 (en) 2002-01-02
DE60101481D1 (en) 2004-01-22
EP1290496B1 (en) 2003-12-10
US6444373B1 (en) 2002-09-03
WO2001098830A2 (en) 2001-12-27
US20020160281A1 (en) 2002-10-31
US6579651B2 (en) 2003-06-17
EP1290496A2 (en) 2003-03-12
DE60101481T2 (en) 2004-10-14

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