WO2001097286A2

WO2001097286A2 - High density three dimensional chip package assembly systems and methods

Info

Publication number: WO2001097286A2
Application number: PCT/US2001/016470
Authority: WO
Inventors: Vince Rogers; Mark W. Roberson; Glenn A. Rinne; Philip A. Deane; Richard Baldwin
Original assignee: Mcnc
Priority date: 2000-06-13
Filing date: 2001-05-22
Publication date: 2001-12-20
Also published as: WO2001097286A3; AU2001274890A1

Abstract

The present invention comprises a number of systems and methods for precisely aligning and spacing microelectronic chips during the fabrication and assembly of three-dimensional microelectronic packages. The present invention precisely aligns and spaces microelectronic chips via an alignment jig comprising two or more opposing walls or surfaces, at least two of which are substantially parallel, and fixed in relation to one another. Support features on the at least two substantially opposing walls of the jig maintain the alignment and spacing of the microelectronic chips placed in the jig. In another embodiment of the present invention, an end effector for a chip pick and place tool includes a vacuum block, including a thermocouple and heating element. Thus, the pressure of the vacuum block may engage and hold a microelectronic chip as the chip is lifted and placed where desired on a substrate. The heating element may be utilized to heat the associated solder bumps to bond the microelectronic chip to the substrate.

Description

HIGH DENSITY THREE DIMENSIONAL CHIP PACKAGE ASSEMBLY SYSTEMS AND METHODS

FIELD OF THE INVENTION The present invention generally relates to microelectronic devices and methods, and more particularly, to methods and systems for the assembly of three dimensional microelectronic packages.

BACKGROUND OF THE INVENTION In the packaging of microelectronic devices, such as packaging integrated circuit chips on printed circuit boards, integrated chips are generally mounted parallel to and facing the printed circuit board such that faces of the integrated circuit chips are adjacent a face of the circuit board. This packaging technology allows a large number of input/output connections between the integrated circuit chips and the substrate (e.g., printed circuit board), especially when solder bump technology is used over the entire face of the integrated circuit chips. This technology, however, limits the packaging density because the large faces of the integrated circuit chips are mounted adjacent the face of the printed circuit board.

In order to increase the packaging density of chips on a printed circuit board, three-dimensional packaging has been proposed, wherein the chips are mounted orthogonal to the circuit board so that edges of the chips are adjacent the face of the circuit board. See, for example, U.S. Patent No. 5,347,428 to Carson et al. entitled "Module Comprising IC Memory Stack Dedicated to and Structurally Combined With an IC Microprocessor Chip," assigned to Irvine Sensors Corporation, hi Carson et al., solder bumps are used to connect the edges, rather than the faces of integrated circuit chips to a substrate. Another three-dimensional packaging technique is described in U.S. Patent No. 5,113,314 to Wheeler et al. entitled "High Speed, High Density Chip Mounting. " In Wheeler et al., a plurality of integrated circuit chips whose active faces are perpendicular to a chip carrier is disclosed. Solder bumps are used to connect pads on the chips to pads on the substrate. Yet another method of assembling three-dimensional IC chip packages is described in U.S. Patent No. 5,432,729 to Carson et al. entitled "Electronic Module Comprising A Stack ofIC Chips Each Interacting With An IC Chip Secured To The Stack. " This patent describes taking a stack of chips that are laminated to one another via a glue or other laminating substance, polishing the lower portion of the stack, applying a metallization layer, and then attaching the stack to a substrate via solder bumps or arched solder columns. Notably, this method results in the chips being mounted perpendicular to the face of the substrate via, and the solder bumps or columns connect the polished and metallized edges of the stacked chips to the substrate. Because the polishing and metallization steps require clean room operations subsequent to the processing of the individual chips however, this method is costly. In addition, the cube-like shape of the stacked chips requires special tooling. hi order to increase the packaging density in three-dimensional chip structures even further, the leaning of integrated to circuit chips was proposed. The leaning of microelectronic chips is not only a highly effective means of increasing the packaging density of three-dimensional chip structures, but allows one to more effectively, efficiently and durably connect the leaning chips to the substrate via solder bumps or arched solder columns. Thus, in order to achieve the novel electrical and computational properties realized through the use of microelectronic chips joined out-of-plane, the assembly of three-dimensional microelectronic leaning chip structures has become desirable in the fabrication process. Of particular importance is the alignment and spacing of the microelectronic chips in three dimensions.

SUMMARY OF THE INVENTION The present invention comprises a number of systems and methods for precisely aligning and spacing microelectronic chips during the fabrication and assembly of three-dimensional microelectronic packages. The present invention precisely aligns and spaces microelectronic chips via an alignment jig comprising two or more sidewalls, at least two of which are substantially parallel and opposing one another, and fixed in relation to one another. Pegs on the lower portions of the walls of the jig engage a substrate. Support features on the at least the two substantially opposing walls of the jig maintain the alignment and spacing of the microelectronic chips placed in the jig. In one embodiment of the invention, the opposing two walls are interconnected by one or more bridging members. For example, the two walls may be configured with a single bridging member in a U- shape, H-shape or with multiple bridging members in the shape of a square or rectangle.

In another embodiment of the invention, the two opposing walls are held at specified distances and orientations relative to one another by two support members. The support members are preferably attached to a superstructure underlying the opposing walls. An alignment jig in accordance with the present invention, with microelectronic chips in situ, may undergo a reflow process, wherein the chips are bonded to the substrate via solder bumps located along the interconnecting edges of the chips and/or the substrate, thus providing both electrical and mechanical interfaces between the chip and substrate. The alignment jig may be removed once the solder has solidified after the reflow step, if desired. In yet another embodiment of the present invention, an end effector for a chip pick and place tool includes a vacuum block, including a thermocouple element and a heating element. Thus, the pressure of the vacuum block may engage and hold a microelectronic chip as the chip is lifted and placed where desired on a substrate. The heating element may be utilized to heat the associated solder bumps to bond the microelectronic chip to the substrate.

The support features in accordance with the present invention may be implemented by a number of structures integral to the alignment jig. The walls of the alignment jig may have parallel and opposing recesses, parallel and opposing ridges, or parallel and opposing pegs, all of which support, space and align microelectronic chips placed in the alignment jig. Proper spacing between the chips may also be achieved through the use of non-functional solder bumps on the faces of chips, the placement of spacer material between adjacent chips, or chip holders.

Advantageously, an alignment jig in accordance with the present invention provides for high density packaging, which is particularly well suited for memory systems. The alignment jig of the present invention can be mass produced using injection molding techniques or by well known metal machining techniques. Further, the alignment jig of the present invention provides for rapid and precise assembly of three dimensional structures having faster heat/cool cycles.

Other features and advantages of the present invention will become apparent to one skilled in the art upon examination of the following drawings and detailed description. It is intended that all such features and advantages be included herein within the scope of the present invention as defined by the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a first alignment jig in accordance with an embodiment of the present invention.

FIG. 2 is a perspective view of a second alignment jig in accordance with an embodiment of the present invention.

FIG. 3 is a perspective view of an end effector in accordance with an embodiment of the present invention.

FIG. 4 is a perspective view of the end effector of FIG. 3 placing a bumped microelectronic chip on a substrate.

FIG. 5 is a side elevational view of a three dimensional microelectronic chip package utilizing various embodiments of a chip spacer according to the present invention for maintaining substantially constant spacing between adjacent microelectronic chips.

DETAILED DESCRIPTION OF THE INVENTION The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the illustrated features are not necessarily drawn to scale, but may be exaggerated for clarity. Like numbers refer to like elements throughout. With reference to FIG. 1, illustrated is an alignment jig 10 in accordance with an embodiment of the present invention. The alignment jig 10 comprises two opposing support walls 12, which are preferably parallel to one another. One or more bridge members 14 interconnect the support walls 12 so as to form a substantially rectangular or square structure. However, an alignment jig in accordance with the present invention may comprise a single bridge member interconnecting the support walls 12 so as to form a substantially U-shaped or H- shaped structure. Further, the alignment jig may include three or more bridge members interconnecting the support walls 12, as may be desired.

The opposing surfaces 16 of the support walls 12 include corresponding chip alignment guides 18, which are grooves in the embodiment illustrated. However, as will be discussed below, the chip alignment guides 18 may take other suitable forms such as a ridges or a peg support system. The corresponding chip alignment guides 18 of respective support walls 12 are configured to receive a microelectronic chip 20, as illustrated. By precisely controlling the design of the chip alignment guides 18, the microelectronic chips 20 may be precisely aligned and positioned with respect to a substrate 22, and more particularly, the routing pads 24. It may be desirable to include jig alignment pins 26 which are integrally formed as a part of the alignment jig 10 and configured to be received within notches fabricated in the substrate 22. However, as will be appreciated by one of ordinary skill in the art, the jig alignment pins 26 may be integrally formed on substrate 22 and configured to be received within notches fabricated in alignment jig 10. Preferably, two or more alignment jig pins are utilized in order to maintain precise registration between the alignment jig 10 and the substrate 22. Utilizing well known microelectronic fabrication techniques, the alignment jig pins 26 and corresponding notches may be fabricated with relatively high precision. The microelectronic chips 20 may be electrically and mechanically coupled to the substrate 22 by arched column solder interconnects, in a manner as generally described in U.S. Patent No. 5,793,116 to Rinne et al., the disclosure of which is incorporated herein by reference as if set forth in full. For example, the surfaces 28 of the microelectronic chips 20 may be bumped at a lower portion adjacent to the substrate 22 and so as to correspond with routing pads 24 which are preferably wettable. Accordingly, during a solder reflow step, the solder bumps will wet the corresponding routing pad so as to form arched solder columns extending between the microelectronic chips 20 and the substrate 22. While the chip alignment guides 18 in the illustrated embodiment place the microelectronic chips 20 at an oblique angle with respect to substrate 22, the microelectronic chips may be held perpendicular to substrate 22 if sufficient solder is provided for forming the arched solder column during the reflow step. For instance, both the routing pads 24 and the microelectronic chips may be bumped, or alternatively, the solder bumps may be provided with elongated pad extensions covered with solder for providing additional solder, as described in U.S. Patent No. 5,793,116. However, when there is not sufficient solder to overhang over to contact the adjacent pad on the substrate, the microelectronic chip may be leaned over with respect to the substrate 22 so that the solder makes contact with the routing pads 24. Lastly, it is further noted that the routing pads 24 may be bumped instead of the microelectronic chips 20. In such cases, the microelectronic chips 20 should be provided with non- bumped wettable pads on the surfaces 28 adjacent to the substrate 22 and aligned with corresponding bumped routing pads 24.

The routing pads 24 are configured in a high density array so as to maximize chip density. The routing pads 24 may be in electrical communication with respective solder bumps 30 having a much coarser gridding for connection to a higher level assembly package, such as a motherboard.

The alignment jig 10 may be fabricated from numerous materials such as plastics or metals. With regard to plastics, the alignment jig 10 may be fabricated at a relatively low cost using well known injection molding techniques. Suitable plastic material maybe liquid crystal polymers loaded with silica crystal fibers. Alternatively, a metal alignment jig may be fabricated using metal machining techniques so as to produce a durable and long lasting alignment jig. Suitable metals for alignment jig 10 may include KOVAR® (a registered trademark of Westinghouse Electric and Manufacturing Company), stainless steel, copper or brass. Regardless of the material utilized for alignment jig 10, it is preferable that the coefficient thermal expansion of the material be less than 15xl0^"6 microns/°C up to 350 °C in order to have adequate dimensional stability at temperatures high enough to melt solder. If the alignment jig 10 is to be left in place following the reflow step, it may be desirable to utilize material that can be easily and inexpensively fabricated into an alignment jig, and which is not conductive, such as plastics, glass, or a dielectric coated material. If the alignment jig is removed following the reflow step, then it may be desirable to utilize metal for fabricating the alignment jig because of its durability and long reuse life. With regard to the dimensions of the alignment jig 10, including the spacing between adjacent chip alignment guides 18, said dimensions will be a function of microelectronic chip size and desired packaging density. It is noted that the fabrication techniques associated with the different materials which maybe utilized for fabricating the alignment jig may limit the chip spacing because of the tolerances required. Outer limits to the chip spacing may be between 50 micrometers to 1 centimeter, though typical chip spacing will fall between 600 micrometers to 2 millimeters. The height of the alignment jig is preferably less than the height of the microelectronic chips 20 when placed in the alignment jig 10. Further, other factors such as cost may effect the dimensions and the configuration of the alignment jig 10, as will be appreciated by those of ordinary skill in the art.

With reference to FIG. 2, an alignment jig 110 in accordance with a second embodiment of the present invention. The alignment jig 110 comprises supporting walls 112 having opposing surfaces 116. The respective opposing surfaces 116 include chip alignment guides 118a-118c. The chip alignment guides 118a comprise a groove fabricated into the surfaces 116, the chip alignment guides 118b comprise extruded ridges, and chip alignment guides 118c comprise extruding pegs. The groove 118a may be formed by milling techniques or well known photolithographic techniques. The extruding ridge 118b may be formed from a mesa that is etched away from the surface 116. The extruded pegs 118b are particularly advantageous in that they minimize the surface contact area, and therefore may provide more efficient cleaning after the reflow step when utilizing flux. However, it will be recognized by those of ordinary skill in the art that the chip alignment guides 118a-118c, may take other suitable forms for providing the necessary structure for precisely aligning and holding microelectronic chips inserted into the alignment jig 110.

Regardless of the configuration of the chip alignment guides 118a-118c, the microelectronic chips may be placed within the alignment jig 110 manually or by computer-assisted machine placement tool. The material and technique utilized to fabricate the alignment jig 110 is substantially similar to that described above with reference to alignment jig 10. Further, if desired, once the microelectronic chip has been placed in the alignment jig 110 so that the microelectronic chip and the substrate are both in contact with the solder that will ultimately bond the two together, ultrasonic energy may be utilized to temporarily tack the microelectronic chip in place. The ultrasonic energy may be applied to the microelectronic chip and/or the substrate to form a temporary bond between the microelectronic chip and the substrate, which is especially strong to hold the microelectronic chip within the alignment jig. Accordingly, utilizing the chip alignment guides 118, a microelectronic chip (not shown) may be inserted into the alignment jig 110 for precise predetermined alignment and spacing between adjacent microelectronic chips and the substrate 122. The jig support members 126 hold the support walls 112 at a specified distance and orientation in relationship to one another. Suitable structures/configuration for the alignment support members 126 are arches, rails or positioning devices attached to the superstructure 140. The material used for the jig support members 126 should be compatible with the temperatures to be used for the reflow process. The substrate 122 may be further connected to a super structure 140, such as a motherboard. As discussed above with reference to alignment jig 10, the configuration of chip alignment guides 118a-118c maybe such that microelectronic chips inserted into the alignment jig 110 may be at oblique angles with respect to the substrate 122, or alternatively, perpendicular to the substrate 122. In addition, the microelectronic chip inserted into the alignment jig 110 may be bumped, and/or the substrate 122 may be bumped. If desired, the jig support members 126 maybe designed to be adjustable or accommodating variances in the size of the microelectronic chips inserted into the alignment jig 110. The jig support members 126 may also be designed for allowing efficient removal of the alignment jig 110 following the reflow step, as maybe desired. Accordingly, an alignment jig 10,110 in accordance with the present invention provides for the efficient assembly of high density three dimensional chip package assemblies. The alignment jig 10,110 is designed to operate in situ during the alignment, fluxing and subsequent reflow processing steps. The alignment jig 10,110 may be left in place following the reflow step, or alternatively, may be removed.

With reference to FIG. 3, an end effector 150 in accordance with an embodiment of the present invention is illustrated. The end effector 150 is configured for picking up and placing bumped microelectronic chips on a substrate and performing a reflow process while holding the chip in situ on the substrate. Once the reflow step has been performed, the end effector 150 releases the microelectronic chip. The end effector 150 comprises a mount 152 and a vacuum block 154, which are separated by a thermal insulating layer 156. The mount 152 is attached to an arm 158 which is preferably fitted to a robotic pick and place tool, as is well known in the industry. A reference position guide 160 aligns the edge of the microelectronic chip when being held by the end effector 150. In the embodiment illustrated, the reference position guide 160 is provided by an exposed portion of the interface surface between the vacuum block 154 and the thermal insulating layer 156. The vacuum block 154 includes a vacuum duct 162 on a side thereof. The vacuum duct 162 which provides the vacuum force for holding a microelectronic chip. The vacuum pressure provided at the vacuum duct 162 is drawn through the end effector 150 and arm 158, which is in communication with a vacuum generating source, as is well known by those skilled in the art. Further, the vacuum block 154 is provided with a first bore 164 and a second bore 166 which are configured to interchangeably receive a heating element 170 and a thermal couple 172.

The configuration of the vacuum duct 162 in the illustrated embodiment is substantially rectangular, though it will be appreciated by those of ordinary skill in the art that the vacuum duct 162 may take other shapes such as square or circle, hi addition, multiple vacuum ducts maybe provided on the surface 174 of the vacuum block 154. However, it is preferred that the vacuum duct 162 the relatively small in comparison to the surface area of surface 174 in order to maximize the contact area of the surface 174 with the microelectronic chip held by the end effector 150 to achieve sufficient thermal conductivity. Further, it is recognized that the force provided by the vacuum drum through vacuum duct 162 is depended upon the surface area of the microelectronic chip exposed to the vacuum, that is, the size of the opening of the vacuum duct 162.

The heating element 170 and thermal couple 172 may be inserted into the first bore 164 and a second bore 166, respectively. The heating element may be any standard electrical heating element capable of providing sufficient heat for melting the solder bumps associated with a microelectronic chip held by the end effector 150. The thermal couple 172 may be utilized to monitor the temperature of the vacuum block 154 during the heating cycle as the heating element 170 ramps the temperature of the vacuum block 154 up to a temperature necessary to melt the solder bumps, and then ramps the temperature down until the solder solidifies. Therefore, the heating element 170 and thermal couple 172 are preferably connected to a control system suitable for such operation, as are well known in the industry. Thus, the heating element 170 heats the vacuum block 154, which in turn heats a microelectronic chip held by the end effector 150, causing the solder bumps associated with the microelectronic chip to melt so as the form arched solder interconnects.

The vacuum block 154 is preferably made of a material having a high coefficient of thermal connectivity, such as brass or other metals. A metal vacuum block 154 can be easily fabricated using metal machining techniques well known to those skilled in the art. In order to insulate the mount 152 and arm 158 from the high temperatures of the vacuum block 154 during the heating cycles, the thermal insulating layer 156 is preferably made of material having a relatively low coefficient thermal connectivity, such as high temperature plastic or ceramic.

As illustrated in FIG. 4, the end effector 150 can be utilized to pick up a bumped microelectronic chip 180 having solder bumps 182 disposed a lower edge thereof, and then precisely placing the microelectronic chip 180 adjacent to a substrate 184. The substrate 184 may include wettable solder pads 186 corresponding to the solder bumps 182. The reference position guide 160 provides a mechanical reference for placing the chip 180 into the end effector 150. As such, the reference position guide should have a close mechanical tolerance for being perpendicular to the end effector to avoid a chip which is rotated. A rotated chip may be deleterious because one end of the chip would make contact with the substrate while the other end with connections may not be in contact with the substrate.

It is understood by those skilled in the arts that optical machine vision techniques can be used to align the chip or chips to the substrate. Although the method utilized may vary according to specific application, generally an image is acquired of the substrate where the position and orientation of the substrate is recorded and an image is acquired of the chip where the position and orientation of the chip is recorded. Using a previously aligned and calibrated placement tool, the operator or machine then orients one or both of the chip and substrate to cause the position and orientation of the chip and substrate to be useful for chip assembly, as desired. Methods of accomplishing the image acquisition include a single camera with split vision optics and dual camera systems.

In addition to bringing a single chip in contact with the substrate, many chips can be aligned in accordance with the present invention. A heated chuck can hold the substrates by a vacuum duct as with the previously disclosed embodiment. The substrate(s) are then brought into contact with the edge oriented chips and the solder is reflowed. This method has the advantage of allowing the use of eutectic bumps on the chip and high-lead solder on the substrate. Following reflow, the vacuum is released and the heated chuck removed. This method minimizes the time-temperature profile experienced by both the eutectic solder and the chips which may be advantageous.

Advantageously, the vacuum duct 162 is positioned on a side surface 174 which allows the end effector 150 to position the microelectronic chip in a perpendicular or oblique angle with reference to the substrate 184. The end effector 150 holds the microelectronic chip 180 in place as the heating element 170 heats the vacuum block 154 to a temperature sufficient for reflowing the solder bumps 182 to wet and form a contact with corresponding solder pads 186. It should be noted, however, that other heat sources can be utilized as an alternative to the heating element 170, such as laser power applied to the respective solder bumps 182. The vacuum block 154, and thus the microelectronic chip 180, are then cooled to allow the solder to solidify forming art solder columns between microelectronic chip 180 and the substrate 184, thereby forming arched solder columns. The solidified art solder columns may then support the microelectronic chip 180 allowing the removal of the end effector 150. This process may be repeated in order to create an array of microelectronic chips attached to the substrate 184 in a three dimensional configuration.

Accordingly, the end effector 150 may provide for a faster heating and cooling cycles, and its relatively small size allows for higher packing density of microelectronic chips. With reference to FIG. 5, an aspect of the present invention provides for the maintaining of a predetermined spacing between microelectronic chips during fabrication and assembly of three dimensional microelectronic chip structures. Specifically, microelectronic chip spacers in accordance with the present invention may be placed between leaning chips to prevent the direct contact between adjacent microelectronic chips. In the illustrated embodiments, chip spacers 190a-

190d are illustrated in FIG. 5. The chip spacers 190a-190d are generally disposed at the distal edge of adjacent microelectronic chips 192, which are connected to a substrate 194 by arch solder interconnects 196 at proximate ends thereof.

Accordingly, the spacing between adjacent microelectronic chips 192 maybe maintained over time and use of the three dimensional microelectronic chip structure. The microelectronic chip spacer 190a comprises non-functional solder bumps placed on the downward-leaning portion of a microelectronic chip so that the bumps may rest upon or be adjacent the upward-facing portion of the immediately adjacent chip. Alternatively, the nonfunctional bumps may be placed on the upward- facing portion of the microelecfronic chip so as to contact or support the downward-leaning portion of the immediately adjacent chip. The microelectronic chip spacer 190b comprises a spacer bar placed between the downward-leaning portion of a microelecfronic chip in the upward-facing portion of an immediately adjacent microelecfronic chip. The microelecfronic chip spacers 190c and 190d comprise a chip holder which connected to an external frame or structure. The chip holder configuration 190c contacts only the lower edge or downward-facing portion of a leaning microelecfronic chip, while the chip holder configuration 190d contacts both the lower edge or downward-facing portion of a leaning chip and the upward edge or upward-facing portion of an immediately adjacent leaning chip.

Many modifications and other embodiments of the invention will come to mind to one skilled in the art to which this invention pertains having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

THAT WHICH IS CLAIMED:

1. A three-dimensional microelectronic chip package assembly system for use in soldering a plurality of microelecfronic chips to a subsfrate comprising: an alignment jig that receives the plurality of microelectronic chips and holds the plurality of microelecfronic chips in precise alignment with respect to one another and the subsfrate wherein said alignment jig comprises: a support structure having opposing surfaces, wherein the surfaces include corresponding chip alignment means for positioning microelectronic chips received by the alignment jig.

2. The assembly system of Claim 1, wherein the chip alignment means comprises a ridge extending at least partially across a surface.

3. The assembly system of Claim 1, wherein the chip alignment means comprises a groove defined by a surface.

4. The assembly system of Claim 1, wherein the chip alignment means comprises pegs extending from a surface.

5. The assembly system of Claim 1 , wherein the alignment jig holds microelecfronic chips at an oblique angle with respect to the subsfrate.

6. The assembly system of Claim 1 , wherein the alignment jig comprises plastic.

7. The assembly system of Claim 6, wherein the plastic has a coefficient of thermal expansion less than approximately 15xl0^"6 micron/°C.

8. The assembly system of Claim 1 , wherein the alignment jig comprises a metal.

9. The assembly system of Claim 1 , wherein the alignment jig comprises a dielectric material.

10. The assembly system of Claim 1, wherein the alignment jig comprises jig position means for aligning the jig with respect to the subsfrate.

11. The assembly system of Claim 1 , wherein the jig positioning means comprises pins that correspond to holes defined in the subsfrate.

12. The assembly system of Claim 1, wherein the jig positioning means comprises holes defined in the alignment jig which correspond to pins on the subsfrate.

13. The assembly system of Claim 1 , wherein the alignment j ig comprises a bridging member interconnecting the two opposing surfaces.

14. An end effector for attachment to a pick and place tool for placing microelectronic chips on a substrate comprising: a mount that is configurable to couple to a pick and place tool; an insulating layer adjacent to the mount; and a vacuum block adjacent to the insulating layer opposite the mount, the vacuum block having a surface defining at least one vacuum duct.

15. The end effector of Claim 14, wherein the vacuum block includes a first bore for receiving a heating element and a second bore for receiving a thermocouple.

16. The end effector of Claim 14, further comprising a reference position guide associated with the vacuum block to align a microelectronic chip.

17. A three dimensional microelecfronic chip packaging comprising: a substrate; a plurality of microelectronic chips mounted to the substrate in a non- parallel relationship relative to the subsfrate; and a chip spacer disposed between adjacent microelectronic chips at a substantially distal edge of the adjacent microelectronic chips to maintain a substantially constant spacing between the adjacent microelectronic chips.

18. The chip package of Claim 17, wherein the chip spacer is a solder bump.

19. A method of assembling a three-dimensional microelectronic chip package whereby microelectronic chips are mounted to a substrate at an acute angle, comprising: placing an alignment jig on the subsfrate, wherein the alignment jig includes chip alignment guides that position respective microelectronic chips; placing a microelecfronic chip in the alignment jig, wherein a first edge of the microelecfronic chip is adjacent the subsfrate, and the first edge further being adjacent a plurality of solder bumps; and reflow the solder bumps to form arched solder interconnections between the microelectronic chip and the subsfrate.

20. The method of Claim 19, further comprising removing the jig after the reflow step.

21. The method of Claim 19, wherein the step of placing the microelecfronic chip includes placing a bumped microelecfronic chip.

22. A method of assembling a three-dimensional microelectronic chip package, whereby microelecfromc chips are mounted to a subsfrate, comprising: picking a bumped microelecfronic chip utilizing a vacuum end effector; placing the bumped microelecfromc chip in a non-parallel relationship relative to the subsfrate, wherein a first edge of the bumped microelecfronic chip is adjacent the subsfrate; heating the vacuum end effector to a sufficient temperature to reflow the solder bumps of the bumped microelectronic chip, thereby forming arched solder interconnects between the microelecfronic chip and the substrate; and releasing the microelectronic chip from the vacuum end effector after the heating step.

23. The method of Claim 22, further comprising the step of monitoring a temperature of the vacuum end effector during the heating step.