WO2001095390A1

WO2001095390A1 - Semiconductor device and method of manufacturing the device

Info

Publication number: WO2001095390A1
Application number: PCT/JP2000/008194
Authority: WO
Inventors: Hiroto Kanao; Hiroaki Kouno
Original assignee: Sumitomo Precision Products Co., Ltd.
Priority date: 2000-06-02
Filing date: 2000-11-20
Publication date: 2001-12-13
Also published as: JP2002057215A; JP4967084B2

Abstract

A semiconductor device capable of increasing the stability of high-speed operation of a circuit by reducing a parasitic capacity and having at least two or more upper and lower layers of wires (1, 2) for connecting elements to each other installed on a silicon substrate having the elements provided thereon, characterized in that columns (3, 4) connected to a lower surface (2d) of the upper layer wire (2) and supporting the upper layer wire (2) are formed, and a space (5) continuing from a clearance (arrow 5a) between the lower layer wires (2) to at least a part of the lower surface (2d) (arrows 5b, 5c) of the upper layer wire (2) is formed.

Description

Specification

Semiconductor device and method of manufacturing the same

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of preventing an increase in parasitic capacitance (wiring capacitance) due to a reduced wiring interval of the same layer and stabilizing a high-speed operation of an integrated circuit. It relates to the manufacturing method. Background art

Conventionally, as a technique for reducing the parasitic capacitance between interconnects, it has become common sense to cover the upper, lower, and interlayer layers of interconnects with an insulating film. Silicon (S ί Ο ₂ ) is used. However, in recent years, the spacing between wirings has been further narrowed, and it has become impossible to reduce the parasitic capacitance as desired by using only an insulator that fills the space between wirings. An increase in parasitic capacitance causes generation of inductive noise, which hinders stable circuit operation especially in a circuit operating at high speed. Therefore, various techniques for reducing the capacitance by providing holes or cavities in the insulator between the wirings have been disclosed. The voids or cavities reduce the capacitance between wirings, reduce the time constant during charging, and guarantee high-speed operation of elements and circuits. FIG. 21 shows an example of a semiconductor device having such a cavity (Japanese Patent Application Laid-Open No. H10-335549), and FIGS. 22 and 23 show the manufacturing method. .

In FIG. 21, insulating films 103 and 104 are formed between the lower wiring 101 and the upper wiring 102, and a cavity is formed between the insulating films 103 and 104. 105 are formed. Buried metal 106 is upper wiring 102 and lower wiring The semiconductor device has a lower wiring or a semiconductor substrate having a semiconductor element below the interlayer insulating film 107. In FIG. 22, the lower wiring 101 is patterned on the interlayer insulating film 107, and the insulating film 103 is formed so as to cover the lower wiring 101 (FIG. 22). (See (a)). This insulating film 103 is, for example, an oxide film. After a plasma oxide film or a bias sputtered oxide film is grown to a thickness of 1.5 / m, the film is formed by a CMP (Chemical Mechanical Polishing) method. , Polishing ■ Flattened to form a 800 nm thick film on the wiring.

Next, the cavity forming opening 108 (0.3 m □) and the via hole opening 109 (0.4 fl mn) are simultaneously formed by the usual photo resist method and anisotropic etching method. (See Figure 22 (b)). If the wiring interval is 0.9 m or more, two cavity forming openings 108 a and 108 b having a width of 0.3 jUm are formed. By performing over-etching, the depth of the cavity forming opening can be formed sufficiently deep down to the lower surface of the lower wiring 101. For example, if the amount of overetching is set to about 80%, the depth becomes about 140 nm.

Next, in the via hole opening 109, a tongue 亍 ^ ¾ to be a buried metal 106 is grown by a CVD method or a Chemical IV apor D Θ position (chemical vapor deposition) method. For example, when WF ₆ is used as a growth gas and reduced with H ₂ or SiH ₄ at about 400 ° C., tungsten grows only on the metal (see FIG. 23 (c)).

On top of this, the insulating film 110 (oxide film: plasma oxide film or bias sputtered oxide film) is reduced in RF power to reduce the embedding property, and the upper part of the space forming opening 108 is closed. Under the conditions that make it easier, interlayer insulation is applied to the entire surface until only the upper part 104 of the space forming opening 108 is sufficiently closed. A film 110 is formed. As a result, a closed cavity 105 is formed in the insulating film 103 between the lower wirings 101 (see FIG. 23D).

Next, the interlayer insulating film 110 is polished and flattened using a wafer polishing technique (CMP) until the buried metal 106 is exposed (see FIG. 23 (3)), followed by a normal photo resist method. Then, an upper wiring 102 is formed by using an etching method.

However, in the conventional example described above, since the cavity 105 is formed in the insulating film 103 in a columnar shape by anisotropic etching, the cavity 105 has a sufficient depth (lower layer) due to excessive etching. It is considered that there is a limit to the reduction of the parasitic capacitance even if it is designed to have a lower level than the lower line of the wiring 101). Other disclosed prior arts (JP-A-2-86146 and JP-A-5-21617) also have anisotropy with respect to an insulator existing between wirings. Since holes or cavities are provided by etching and other processes, there is a limit to the reduction of parasitic capacitance due to space reasons, and it is not possible to sufficiently cope with increasingly severe design rule miniaturization. In. In addition, as the technology for forming structures of semiconductor devices such as transistors progresses in three dimensions, three-dimensional wiring (such as between wiring in the same layer, between wiring in upper and lower layers, and between wiring in twisted positions, etc.) Also, it is essential to reduce the parasitic capacitance between elements.

The present invention has been made in view of the above-described problems of the present invention, and a main object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can dramatically reduce parasitic capacitance not only between planar wiring but also three-dimensional wiring. Is to do. Another object of the present invention is to obtain a stable semiconductor device by increasing the manufacturing accuracy of the support for supporting the upper layer wiring, and to damage wiring and elements when forming a space for reducing parasitic capacitance. The goal is to provide a process without any problems. Disclosure of the invention

According to the present invention, in a semiconductor device provided on a silicon substrate on which a plurality of elements are provided so that at least two wirings connecting the elements are formed at least vertically above and below, the semiconductor device is connected to a lower surface of the upper wiring. A pillar that supports the upper wiring is formed, and a continuous space is formed from a gap between the lower wirings to at least a part of a lower surface of the upper wiring. The support forms a space between the same layer and the upper and lower layers. This space extends three-dimensionally between the wirings (between the same layer, upper and lower layers and between twisted positions), and the parasitic capacitance can be sufficiently reduced even if the wiring interval is narrowed.

In the present invention, the support is preferably an insulator.

By forming the pillars with an electrical insulator, it is possible to sufficiently reduce the parasitic capacitance when narrowing the space between the wirings, while ensuring insulation between the wirings. At the points where electrical connection is desired between the upper and lower layers (including the vertical relationship separated by at least one layer), conductive metal is provided in a columnar shape, and the columnar conductive metal does not need to support the upper wiring. In the present invention, when the support is made of an insulating material, the support is provided on the lower wiring and supports the upper wiring, And a second support supporting the upper layer wiring at a portion on the silicon substrate which is not provided, and it is preferable that at least one of the first supports has a metal for conduction embedded therein.

The upper and lower layers are electrically connected by the metal for conduction embedded in the pillar.

On the other hand, in the present invention, it is preferable that the support is made of a conductor. In this case, the pillars are made of a conductor, so that the upper and lower layers are electrically connected. It can also serve as a wiring for connection. Therefore, the structure is simplified, and in the manufacturing method, the step of burying a metal for conduction can be omitted. In the case of a metal pillar, it can be provided on an insulating layer to be insulated.

Further, in the present invention, it is preferable that a concave portion is formed on the surface of the substrate between the elements, and the space is continuous within the concave portion.

By forming the concave portion between the elements, the insulation between the elements can be increased, and the parasitic capacitance can be reduced. Further, miniaturization between elements can be promoted.

In the case where the inter-element concave portion is provided, it is preferable to form an etching-resistant film on the inner surface of the inter-element concave portion during the semiconductor device manufacturing process and before the etching process.

By forming an etching-resistant film on the inner surface of the inter-element concave portion, the element surface is not damaged during etching. In addition, since the etching does not proceed in the lateral direction of the silicon substrate, it is easy to control the dimensions between the elements.

Further, the present invention is characterized in that a gettering material is provided in the space between the wirings.

Gettering materials are substances that have the effect of adsorbing and removing gas molecules from the gaseous phase, ie, the function of pumping out. As such, barium, magnesium, calcium, titanium, tantalum, zirconium, vanadium, and yttrium, which are commonly known, can be used. In the present invention, by being placed in the space, after the semiconductor device is completed, that is, after the space is formed, the exhaust gas discharged from the material in contact with the space is adsorbed to prevent the outgas from being stored, and the space is evacuated. The purpose is to increase the degree. Realization of high vacuum promotes reduction of parasitic capacitance. Furthermore, corrosion and wiring deterioration due to outgas can be prevented, The life of the semiconductor device can be extended.

In the present invention, as a gettering material, a solid support is provided on an interlayer insulating film or a support for the gettering material in a space between wirings, and the gettering material can be effective after manufacturing a semiconductor. It is preferable to use titanium, zirconium, yttrium and the like. In addition, it is preferable that these are arranged in such a shape that the surface area is maximized when they are arranged. Further, when titanium is used, the plasma used for the isotropic etching is preferably SF ₆ gas.

In the present invention, there is provided a capping layer which covers the upper and lower wirings from above the uppermost wirings of the uppermost layer and hermetically closes a space in which the gettering material is provided.

According to the present invention, since the space is sealed by the cabbing layer, the gas adsorbing action of the gettering material in the space works effectively, and the degree of vacuum in the space is increased.

Next, as a method of manufacturing a semiconductor device described above, first, a manufacturing method of the present invention for manufacturing a semiconductor device in which a metal for conduction is buried in a pillar made of an insulator,

(a) forming the lower wiring on an interlayer insulating film provided on the silicon substrate;

(b) forming a sacrificial layer between the lower wirings and so as to cover the upper surface thereof;

(c) forming a photoresist film by photolithography in a region other than the region where the pillars of the upper wiring are formed;

(d) etching the sacrificial layer in the pillar formation region;

(Θ) An insulating film is formed and buried in the etched region to form a pillar. Forming,

(f) Forming a contact hole opening pattern mask for embedding a metal for conducting the upper wiring with one or more lower wirings below the lower wiring, and etching the support and / or sacrificial layer in the metal embedding region. Forming a contact hole by using

(g) a step of embedding a metal in the etched contact hole;

(h) forming the upper wiring layer;

(i) a step of isotropically etching the sacrificial layer to form a space in a portion other than the column between the upper and lower wirings, between the upper and lower wirings, and between the wirings in a twisted positional relationship;

It is characterized by including.

The step (h) of forming the upper wiring layer includes a step of forming a metal film for the upper wiring after removing the contact hole opening pattern mask and burying the buried metal, and forming an extra metal film according to the wiring pattern. And etching a critical portion. In addition, a method conventionally used as a method for forming a wiring layer (metal film) can also be used.

In this method, a photoresist film (mask) is formed by a photolithography method, and an insulating film is formed and buried in a sacrificial layer that has been etched in a pillar shape, thereby forming a pillar. A column can be formed. Also, after the pillars are formed, all the sacrificial layers are removed by isotropic etching to form spaces, so that the molding accuracy is high.

On the other hand, in the manufacturing method of the present invention for manufacturing a semiconductor device having conductive pillars, the step (g) of embedding a metal in the etched contact hole and the step (h) of forming the upper wiring layer Same as forming It may be performed at a time.

Since the buried metal and the upper wiring are both conductive substances and can be formed of the same material, the steps (g) and (h) are performed simultaneously to further simplify the steps. be able to.

Further, as a method of manufacturing a semiconductor device in which the support is a conductor, the manufacturing method of the present invention includes:

(d) etching the sacrificial layer in the pillar formation region;

(e-1) a step of forming and embedding a metal in the etched region to form a conductive support;

(h) forming the upper wiring layer;

It is characterized by including.

The manufacturing method is simplified as compared with a semiconductor having pillars made of an insulator.

In the above-mentioned manufacturing method, if the buried metal and the upper wiring are formed of the same material, the above-mentioned (e-1) and (h) steps can be performed simultaneously, and the steps are further simplified. .

In addition to the above-described method for manufacturing a semiconductor device, the present invention further comprises, after the step (i), (j) a step of forming a cabling layer on the uppermost layer upper wiring so as to hermetically close the space.

It is preferable that

According to this method, the space made airtight by the caving layer is sucked into vacuum by the gettering material.

Further, as a method of manufacturing a semiconductor device provided with an inter-element isolation recess, the method of manufacturing the semiconductor device according to the present invention includes the following steps:

(a-1) A photoresist mask for forming a through hole for exposing a region for forming an element isolation recess of the silicon substrate in the interlayer insulating film is formed on the interlayer insulating film and the lower layer. A step of forming the wiring on the wiring by photolithography,

(a-2) The through hole is formed by etching the interlayer insulating film in a region that is not covered with the photoresist mask, and a recess forming region for element isolation of the silicon substrate under the interlayer insulating film through the through hole. And (a-3) a step of removing the photoresist mask formed in the step (a-1).

Is inserted.

In this method, prior to the step (b), the lower wiring is covered with a sacrificial layer, the interlayer insulating film under the lower wiring is etched in the steps (a-1) to (a-3) prior to the step (b). A region for forming the separation recess is exposed, and a sacrificial layer is formed on this region in step (b). By doing so, at the time of the isotropic etching in the final (i) step, the sacrificial layer is removed to form a space, and at the same time, the region is dug down to form a recess for element isolation. You. Therefore, the process can be simplified. Further, as a method of manufacturing a semiconductor device in which an etching-resistant film is formed in a recess for isolation between elements, the manufacturing method of the present invention comprises the following steps:

(a-1-1) forming a photo-resist mask for forming an inter-element isolation recess in the silicon substrate on the interlayer insulating film and the lower wiring by photolithography;

(a-2-1) Etching the area not covered with the photo resist mask, penetrating the interlayer insulating film above the element isolation recess forming area, and furthermore, passing the silicon substrate immediately below it to a predetermined depth. Drilling down to form an inter-element isolation recess,

(a-2-2) forming an etching-resistant film on the inner surface of the inter-element isolation recess;

(a-3-1) a step of removing the photo resist mask formed in the step (a-1-1)

Has been introduced.

In this method, the anisotropic etching in the (a-2-1) step is controlled, and simultaneously with the etching of the interlayer insulating film, the element isolation region of the silicon substrate immediately thereunder is anisotropically etched. In addition, it is possible to form the recess for element isolation at a predetermined depth. In addition, an etching-resistant film (for example, an oxide film) is formed on the inner surface of the concave portion, so that an etching-resistant effect can be exerted on the etching for removing the sacrificial layer in the final (i) step. Therefore, the device is not damaged, the dimensional accuracy is improved as a result, and it is possible to cope with further miniaturization of design rules.

In the manufacturing method of the present invention, it is preferable that the sacrificial layer is a silicon layer.

If it is a silicon layer, it can be easily removed using isotropic etching In this case, damage to wiring and elements can be reduced. For example, by providing appropriate etching conditions, a material other than silicon can have a selectivity of 100 or more (500 or more under the most preferable conditions). Therefore, damage to the portions such as the wiring and the pillars in contact with the formed space is very small.

Further, in the manufacturing method of the present invention, it is preferable that the sacrificial layer is a resist layer.

Even when a resist layer is used as the sacrificial layer, the semiconductor device of the present invention can be similarly formed.

Further, as a method of manufacturing a semiconductor device having a gettering material in the same layer as the lower layer wiring, the manufacturing method of the present invention includes:

(I) a step of forming a mask for forming a gettering material,

(Iii) forming a gettering material film, and

(m) removing the gettering material forming mask to obtain a gettering material layer

Has been introduced.

By this method, a gettering material can be provided on the interlayer insulating film in the same layer as the lower wiring. Also, a gettering material can be provided in the same layer as the upper layer wiring in combination with a manufacturing method described later.

As a manufacturing method of providing a gettering material on the same layer as the upper layer wiring, the manufacturing method of the present invention includes:

(I) a step of forming a mask for forming a gettering material,

(Ii) forming a gettering material film, and

Has been introduced. In this method, a pillar or the like is formed on an interlayer insulating film in the same layer as the upper layer wiring, similarly to the upper layer wiring, and a gettering material is disposed thereon. As a matter of course, in one space, two or more wirings may be provided in combination with a wiring in the same layer as the lower wiring and a wiring in the same layer as the upper wiring. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a sectional view showing a first embodiment of the semiconductor device of the present invention. FIG. 2 is a sectional view showing a second embodiment of the semiconductor device of the present invention. FIG. 3 is a sectional view showing a third embodiment of the semiconductor device of the present invention. FIG. 4 is a sectional view showing a fourth embodiment of the semiconductor device of the present invention. FIG. 5 is a sectional view showing a fifth embodiment of the semiconductor device of the present invention. FIG. 6 shows the first half of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 7 is the second half of the continuation of the manufacturing method of FIG.

FIG. 8 illustrates a method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 9 shows the first half of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 10 shows the second half of the continuation of the manufacturing method of FIG.

FIG. 11 shows the first half of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.

FIG. 12 is a diagram showing the latter half of the manufacturing method of FIG.

FIG. 13 is a sectional view showing a sixth embodiment of the semiconductor device of the present invention. FIG. 14 is a sectional view showing a semiconductor device of the seventh embodiment of the present invention. FIG. 15 is a diagram illustrating the first half of the method of manufacturing the semiconductor device according to the sixth embodiment of the present invention.

FIG. 16 shows an intermediate part of the manufacturing method of FIG.

FIG. 17 shows the latter half of the manufacturing method of FIG.

FIG. 18 illustrates the first half of the main part of the method for manufacturing a semiconductor device according to the seventh embodiment of the present invention.

FIG. 19 illustrates the latter half of the main part of the manufacturing method of FIG.

FIG. 20 illustrates a configuration and a manufacturing method of a semiconductor device according to an eighth embodiment of the present invention.

FIG. 21 is a cross-sectional view illustrating an example of a conventional semiconductor device.

FIG. 22 is a diagram showing a first half of a method of manufacturing the conventional semiconductor device of FIG. 21.

FIG. 23 is a diagram showing the latter half of the conventional manufacturing method of FIG. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings. 1 to 5 are cross-sectional views showing an embodiment of the semiconductor device of the present invention and first to fifth embodiments, respectively. 6 and 7 show a method of manufacturing the first embodiment (semiconductor device shown in FIG. 1) of the present invention. In addition, by adopting FIG. 8 instead of FIG. 7, and through the steps of FIG. 6 and FIG. 8, a third embodiment (semiconductor device shown in FIG. 3) of the present invention can be obtained. 9 and 10 show a method of manufacturing the fourth embodiment (semiconductor device shown in FIG. 4) of the present invention, and FIGS. 11 and 12 show a fifth embodiment of the present invention. 6 shows a method of manufacturing the embodiment (semiconductor device shown in FIG. 5).

Further, FIGS. 13 to 20 illustrate the present invention having a gettering material in a space, and FIG. 13 shows that the gettering material is provided in the same layer as the lower wiring. FIG. 14 is a cross-sectional view of a sixth embodiment of the present invention, in which FIG. 14 is a cross-sectional view of a seventh embodiment of the present invention in which a gettering material is disposed in the same layer as the upper layer wiring. 17 show a method of manufacturing the sixth embodiment (semiconductor device shown in FIG. 13), and FIGS. 18 and 19 show a method of manufacturing the seventh embodiment (the semiconductor device shown in FIG. 14). Device). FIG. 20 shows the configuration and manufacturing method of the embodiment of FIG.

In FIG. 1, a lower wiring 1 is provided on an interlayer insulating film 7, and an upper wiring 2 is supported on the interlayer insulating film 7 or the lower wiring 1 by columns 3 and 4. The second support 3 is on the interlayer insulating film 7 and supports the upper wiring 2, and the first support 4 is on the lower wiring 1 and stands upright to support the upper wiring 2. The upper wiring 2 is lifted by the first and second pillars 3 and 4, and a space 5 is formed between the upper and lower wirings 1 and 2. The space 5 is 5 a between the side surfaces 1 a and 1 b of the adjacent lower wiring 1, and between the upper surface 1 c of the lower wiring 1 and the lower surface 2 d of the upper wiring 2 between directly above and immediately below. A three-dimensional space having b and 5c between the lower wiring 1 and the upper wiring 2 which are geometrically twisted.

In FIG. 1, the columns 3 and 4 are formed of an electrical insulator, and the upper and lower layers 1 and 2 are electrically connected by the metal 6 embedded in the first column 4. The metal 6 is appropriately provided at a necessary place. In FIG. 2, a metal 16 electrically connects the upper and lower layers 1 and 2. In the second embodiment, the upper wiring 2 is sufficiently supported by the columns 3 and 4, and the thickness of the metal 16 is not limited. However, it is also possible to use the metal 16 as a substitute for the strut with an appropriate thickness.

Further, in FIG. 3, the pillars 53 and 56 are made of a conductor and have an appropriate thickness. The pillars 5 6 provided on the lower wiring 1 Also plays the role of electrically connecting 1 and 2. Parts that do not need to be electrically connected are erected as appropriate on the insulating film, like the pillars 53.

1 to 3, only the upper and lower two-layer wirings 1 and 2 are shown on the interlayer insulating film 7, but the present invention is not limited to this. Naturally, it includes layers and layers, in which case they are called upper-layer wiring or lower-layer wiring in a vertical relationship. This is the same in FIG.

Upper and lower layer wirings 1 and 2 are made of aluminum (AI), aluminum alloy, copper (Cu), tungsten (W), tungsten silicide (WSi), titanium nitride (（ί Ν), and titanium silicide (TiS). i) or a single body or a laminate. The same applies to buried metal 6 (see Fig. 1) and conduction metal 16 (see Fig. 2).

The pillars 3 and 4 are made of a material having a low dielectric constant such as SiO _x N _x , SiO _x , SiO OF, and amorphous fluorocarbon (a — C: F) when made of an insulating material. Is preferred. Further, it is preferable that the material be able to secure the strength capable of supporting the upper wiring. .

The pillars 53, 56 (see Fig. 3) formed by conductors are made of aluminum (AI), aluminum alloy, copper (Cu), tungsten (W), tungsten silicon, as well as the upper and lower wirings 1, 2. It is composed of a simple substance or a laminated body such as side (WS i), titanium nitride (T iN), and titanium silicide (T iS ί).

The interlayer insulating film 7 is, for example, an oxide film such as a plasma oxide film or a bias sputter oxide film.

In the case of a multilayer structure in which upper and lower wirings 1 and 2 are sequentially stacked via an interlayer insulating film 7, as shown in FIG. 4, a metal 17 for conduction is embedded in the interlayer insulating film 7. Is done. Although not shown, the second support 3 and the layer A metal may be buried in the inter-insulating film 7 to connect the upper wiring 2 and the upper wiring 2 thereon.

FIG. 4 shows a semiconductor device according to a fourth embodiment of the present invention, in which a through hole 8 is provided in an interlayer insulating film 7, and an inter-element isolation recess 10 provided in a silicon substrate 9 immediately below. The through holes 8 communicate with each other. The inter-element isolation recess 10 is provided to enhance the insulation between the elements, and, like the space 5, may be a space or a space closer to a vacuum than a space filled with an insulator. preferable. The through hole 8 is provided for forming the concave portion 10 for isolation between elements.

FIG. 5 shows a fifth embodiment of the semiconductor device of the present invention. In addition to the semiconductor device shown in FIG. 4, an etching resistant film 11 is further formed on the surface of the recess 10 for element isolation. Have been. The etching-resistant film 11 is for preventing the concave portion 10 from being eroded during the manufacturing process.

Examples of the etching resistant film 11 include SiO _x N _x and SiO _x . The etching resistant film 11 can be formed by irradiating oxygen plasma under appropriate conditions without removing the resist mask when etching the interlayer insulating film.

Next, a method for manufacturing the first embodiment (see FIG. 1) and the second embodiment (see FIG. 2) of the semiconductor device of the present invention will be described with reference to FIGS.

In FIG. 6, first, (a) the lower wiring 1 is formed on the interlayer insulating film 7 In this (a) step, for example, a simple substance or a laminate of the above-described material such as an aluminum alloy or copper is patterned and etched. And so on to form the lower wiring 1. For the formation, for example, using a DC magnetron sputtering apparatus, the DC voltage is set to about 1 kW, and the gas to be used is Ar (plasma). ), The flow rate is about 0.1 liter per minute (however, all volumes are in the standard state (0 ° C, 0.1 Pa (1 atm))), and the pressure in the reaction chamber is reduced. Approximately 3 Pa, and the target is AI. After that, an extra portion of the AI thin film formed by sputtering is removed by forming a resist mask and subsequent metal etching (anisotropic dry etching) to obtain the AI wiring (lower layer wiring). In addition, CVD, plating, etc. are also possible. Note that the upper wiring can be formed in a similar manner. Further, the above method is also effective for burying a metal in a contact hole.

Next, (b) a sacrificial layer 22 is formed so as to cover the lower wiring 1.

The sacrificial layer 22 is formed, for example, by forming amorphous silicon. This film formation, for example, by low pressure CVD apparatus, a gas used as the S i H ₄ and A r (or H _2), S i H about 0.0 5-0 a flow rate of _4.2 Li Tsu Torr The Ar flow rate is about 0.5 to 2 liters per minute, the pressure in the reaction chamber is several OPa, and the substrate temperature is about 350 ° C or less and 150 ° C or more. I do.

Next, (c) the sacrificial layer 22 is planarized by a method such as CMP (Chemical Mechanical Polishing), and a photoresist mask 23 is formed. Next, (d) the sacrificial layer 24 not covered by the mask 23 is removed by etching. This etching is preferably anisotropic etching from the viewpoint of dimensional control. For example, an ICP-RIE device (inductively coupled plasma-reactive ion etching (InductivΘIyCupIθdPlasma) the R eactive I on E tching)) , about 1 2 0 0 W coil, the platen was about 3 0 W, the pressure in the reaction応室about 2. 6 7 P a, it SF ₆ and Furuoroka one Bongasu It is preferable to use a flow rate of about 0.1 liter per minute and about 0.05 liter per minute. Next, in FIG. 7, (Θ) After removing the mask 23, an insulating film is buried in the dug down sacrificial layer portion 24 to form a pillar 25. For the formation of the support 25, a Si ₂ film is preferably formed. This film is ECR-CVD equipment! ^ - The (E lectron C yclotron R Θ sonanc Θ p I asma CVD apparatus), 〃 wave power of about 1 k W, U I tail current of about 2 OA, the use gas S i H ₄ 0 ₂ and A r The flow rates were about 0.01 liter per minute, about 0.02 liter per minute, and about 0.05 liter per minute, respectively, and the pressure in the reaction chamber was X ¹ 0- 1 P a, the substrate temperature, about 3 0 0 ° C over 4 5 0 ° C or less, then the RF power and about 2 0 0 W, strut 2 which is formed by (f) said step A photoresist mask 27 is formed on 5 and the remaining sacrificial layer 22, and a contact hole 26 is formed by performing anisotropic etching. Anisotropy Etsuchin grayed in this case, depending on the material of the support post 2 5, as described above, when forming at S i O ₂ film, the anisotropic etching of S i O ₂ film Do. This is achieved, for example, by using an ICP-RIE device to set the coil to about 100 W, the platen to about 500 W, the pressure in the reaction chamber to about 0.33 Pa, and fluorocarbon gas to the standard state. At a flow rate of about 0.02 liters per minute. Although not shown, the contact hole is not limited to the inside of the column 25, and may be formed in the sacrificial layer 22 if necessary. In that case, the production method is determined in consideration of both the materials of the support 25 and the sacrificial layer 22.

Next, (g) the photoresist mask 27 is removed, and the metal 6 is buried in the contact hole 26. This padding, ECR-by CVD equipment, a wave power of about 1 k W, about 2 0 A coil current, and the and the WF ₆ using gas H ₂ and A r, the flow rate of about respectively 0.0 1 liter per minute and about 0.02 liters per minute and about 0.05 liters per minute The pressure is about 0.7 Pa, the substrate temperature is about 300 ° C or more and 450 ° C or less, and the RF power is about 20 OW.

Next, (h) the upper wiring 2 is formed. The upper wiring 2 can be formed by the same method using the same material as the lower wiring 1 described above, but the material and manufacturing method of the lower wiring 1 and the upper wiring 2 may be different in one semiconductor device. (I) A space 5 is formed by etching the sacrificial layer 22. For this, isotropic etching is preferable from the viewpoint of facilitating etching under the upper wiring and between the upper and lower layers. For example, by using SF ₆ plasma, the ICP (inductively coupled plasma) conditions, the coil about 6 0 OW, the bra Ten to about 5 W, the pressure in the reaction chamber to about 2. 7 P a, and use gas Preferably, the flow rate is SF ₆ , about 0.1 liter per minute. In addition, under the ECR conditions, the microwave power, the coil current, and the flow rate of SF ₆ and Ar of the gas used were about 0.05 liter and about 1 kW, respectively. Torr per minute and about 0.05 liter per minute, the pressure in the reaction chamber is about 0.7 Pa, and the substrate temperature is about 300 ° C or more and 450 ° C or less.

Note that XeF ₂ gas can be used for isotropic etching for removing the sacrificial layer 22. In that case, the pressure in the reaction chamber should be about 0.4 Pa or less.

Step (g) (formation of buried metal 6) and step (h) (formation of upper wiring 2) can be performed simultaneously, in which case the material of buried metal 6 and upper wiring 2 is aluminum (AI). , Aluminum alloy, copper (Cu), tungsten (W), tungsten silicide (WSi), titanium nitride (TiN), titanium silicide (TiS i), etc. It is formed by a notter method or a CVD method.

In the present invention, the sacrificial layer is used for forming the above-described amorphous silicon film. Not limited to For example, a resist (model number AZ135) can be used as the sacrificial layer. In this case, either isotropic or anisotropic resist etching can be used. When using the isotropic etching, the conditions, for example, a coil about 6 0 0 W, the platen about 1 0 W, about the pressure in the reaction chamber 5. 3 2 P a, the use gas and flow rate 0 _2, approximately 0.0 3 liters per minute. In the case of anisotropic etching, the coil is about 600 W, the platen is about 15 W, the pressure in the reaction chamber is about 0.27 Pa, the gas used and the flow rate are O ₂ , and about 0.02 Torr per minute. In addition, conventionally used methods can be appropriately used.

Next, a method for manufacturing a semiconductor device according to a third embodiment (see FIG. 3) of the present invention will be described. The first half of the method of manufacturing the semiconductor device is the same as the steps (a) to (d) shown in FIG. The second half, (e-1) step, (h) step and (i) step will be described with reference to FIG.

In FIG. 8, after removing the (Θ-1) mask 23 (see FIG. 6), a conductor 28 is formed by embedding a conductor in the dug down sacrificial layer portion 24. The conductive pillar 28 can be formed by a similar method using the same material as the upper and lower wirings 1 and 2. Subsequently, (h) upper wiring 2 is formed. Similarly, the upper layer wiring 2 can be formed by the same method using the same material as the lower layer wiring 1 described above. (I) The step of forming the space 5 by etching the sacrificial layer 22 is also included. It is the same as FIG.

In the manufacturing method shown in FIG. 8, the step of forming the pillar 28 of ( _θ -1) and the step of forming the upper layer wiring 2 of (h) can be performed simultaneously.

In the manufacturing process in FIG. 8, the steps (f) and (g) for burying the metal 6 for electrically connecting the upper and lower wirings 1 and 2 in FIG. 7 are omitted.

Next, a step of forming a recess 10 for isolation between elements (see FIGS. 4 and 5) is described. This will be described with reference to FIGS. 9 to 12. There are two methods for forming the recess 10 for element isolation. The first method is to etch simultaneously with the removal of the sacrificial layer 22. The second method is a method of etching simultaneously with the interlayer insulating film 7. In the first method, isotropic etching is used to remove the sacrificial layer 22. Therefore, it is difficult to accurately control the depth of the concave portion. However, the manufacturing method shown in FIGS. It can be easily added to the process or the process shown in FIGS. In the second method, the depth of the concave portion can be accurately controlled by using anisotropic etching when forming the penetration hole 8 in the interlayer insulating film 7, but the final step (i) When removing the sacrificial layer 22 with, care must be taken not to erode the recess. Therefore, as in the fifth embodiment shown in FIG. 5, an anti-etching film 11 is provided to protect the inner surface of the concave portion 10 in preparation for the final step (i).

FIGS. 9 and 10 show the above-described first method, that is, the manufacturing method of the fourth embodiment shown in FIG.

In FIG. 9, an interlayer insulating film 7 is provided on a silicon substrate 9. The metal 17 is appropriately buried in the interlayer insulating film 7 to electrically connect the element and the lower wiring 1. _(A) forming a lower layer wiring 1 is the same as FIG.

Next, (a-1) the interlayer insulating film 7 and the lower wiring are removed except for a portion 7a above the silicon insulating film 9 except for a portion 7a located above the silicon insulating substrate 9 immediately below the interlayer insulating film 7 in order to expose the concave portion forming region 1 O a. 1 is covered with a mask 30 such as a photoresist mask.

Next, (a-2) the interlayer insulating film 7 is etched. Etching is anisotropic etching. ICP-RIE uses a coil of about 1 OOOW, a platen of about 500 W, a reaction chamber pressure of about 0.33 Pa, and a gas used of fluoro. With carbon gas, the flow rate can be about 0.02 liters per minute.

Next, (a-3) the mask 30 is removed. A through hole 8 is formed in the interlayer insulating film 7, and an inter-element isolation recess forming region 10 a of the silicon substrate 9 is exposed.

Subsequently, the steps (b) to (h) in FIG. 10 are the same as those in FIGS. 6 and 7, but in the final step (i-1), isotropic etching is performed, and the sacrificial layer 2 Along with the removal of 2, the silicon substrate 9 is dug down from the exposed inter-element separation recess forming region 1 O a to form the inter-element separation recess 10.

FIGS. 11 and 12 show the above-described second method, that is, the manufacturing method of the fifth embodiment shown in FIG. The step (a) in FIG. 11 is the same as in FIG. 6 and FIG.

Next, in FIG. 11, (a—1—1) the interlayer insulating film 7 and the lower wiring 1 are removed except for a portion 7a above the silicon substrate 9 to form a recess 10 for element isolation in the silicon substrate 9. Cover with a mask 30 such as a photoresist mask. Next, (a-2-1) the interlayer insulating film 7 and the silicon substrate 9 immediately below the interlayer insulating film 7 are etched to form recesses for element isolation. The etching is anisotropic etching similarly to the step (a-2) in FIG. 9, but is appropriately controlled so that the depth of the recess 10 for element isolation becomes a predetermined value.

Next, (a-2-2) an etching-resistant film 11 is formed on the inner surface of the concave portion 10 for isolation between elements. Examples of the material of the etching resistant film 11 include SiO _x N _x and SiO _x . This etching resistant film 11 can be formed by performing oxygen plasma irradiation under appropriate conditions without removing the resist mask 30 when etching the inter-layer insulating film 7. When forming the through hole 8 in the interlayer insulating film 7, anisotropic etching is used, so that the recess 10 It is easy to control the depth, and an excellent semiconductor device can be manufactured accurately.

Next, in FIG. 12, the (a-3-1) mask 30 is removed. Hereinafter, steps (b) to (〜) are the same as steps (b) to (i) shown in FIGS. 6 and 7, but in the final step (i), the etching resistant film 11 The semiconductor element in the vicinity of the element separating recess 10 is not adversely affected by isotropic etching when removing the sacrificial layer 22.

In the above-described embodiment of the manufacturing method, the low pressure CVD method and the ECR-CVD method are used, but other CVD methods (thermal CVD method (normal pressure CVD method), plasma CVD method, optical CVD method, ICP (inductively coupled plasma method)) are used. The same effect can be obtained by using the CVD method, the HELI-one CVD method, the SWP (Surface Wave Plasma) -CVD method, other CVD methods, and other HDP (high-density plasma) -CVD methods. The same effect can be obtained by using a sputtering method or a plating method instead of the CVD method. Further, in this embodiment, the ICP-RIE method is used for the etching method, but other RIE methods (RIE method using the plasma method used in the aforementioned CVD method, DRM-RIE method) are used. The effect is the same.

In the present invention, as shown in FIGS. 13 and 14, a gettering material 50 is arranged in the space 5 described above, and a camping layer 52 is provided on the uppermost wiring. In addition, the art gas can be removed from the space 5, and the degree of vacuum in the space can be increased. FIGS. 13 and 14 show the gettering material 50 arranged in the space 5 of the first embodiment shown in FIG. 1. Naturally, the embodiment shown in FIGS. It can be arranged in the space 5 in the same way. The same applies to the manufacturing method. Among them, the structure and manufacturing method of the embodiment in which the gettering material 50 is provided in the space 5 of the embodiment shown in FIG. 4 will be described with reference to FIG. In FIG. 13, the gettering material 50 is provided on the interlayer insulating film 7. In FIG. 14, the gettering material 50 is provided on the support 51. The support 51 may be an insulator or a conductor. The space 5 becomes a hermetically closed space when the cabling layer is provided and the semiconductor device is completed. Therefore, by arranging a substance having a function of adsorbing gas molecules, such as the gettering material 50, the gas originally existing in the space 5 and the gas discharged from the material after the semiconductor device is completed (au) Can be adsorbed and removed from the space 5, and the degree of vacuum in the space 5 can be increased. By increasing the degree of vacuum, the dielectric constant of gas between wirings can be reduced, and as a result, the capacitance between wirings can be further reduced. Further, since corrosive gas can be eliminated, the life of the semiconductor device can be extended.

Examples of the gettering material include barium, magnesium, calcium, titanium, tantalum, zirconium, vanadium, and yttrium. It is preferable to use titanium, zirconium, yttrium, or the like. These are preferably arranged in such a shape that the surface area is the largest when they are arranged. Further, when titanium is used, the plasma used for isotropic etching for removing the sacrificial layer 22 when forming the space 5 is preferably SF ₆ gas.

Kiyabbingu layer 5 2 is an insulating film, the material, in addition dioxide Kei element (S ί Ο _2), fluorine (F) Moshiku the force one carbon (C) containing oxide film (S i OF, Preferred are S i OC), organic SOG, porous SOG, organic polymer, amorphous fluorocarbon (a-C: F), silicon nitride (S i N) and the like.

Next, based on FIGS. 15 and 17, the semiconductor device shown in FIG. Embodiment 6) will be described.

In FIG. 15, (a) the step of forming the lower wiring 2 is the same as that of FIG. 6. Next, in order to dispose the gettering material 50 at an appropriate position on the interlayer insulating film 7, apply (a—I—1) the resist film 31 a and cure it. — 2) Pattern by resist exposure to form a photo resist mask 31. Next, (a-Π) a gettering film 32 is formed. This formation is preferably performed by a sputtering method, for example, by using titanium as a target and under argon plasma. Since the gettering film 32 has an appropriate thickness, the mask 31 is removed (a- （). Hereinafter, in FIGS. 16 and 17, the steps (b) to (i) are the same as the steps (b) to (i) shown in FIGS. 6 and 7.

The cabling layer 52 is formed so as to cover the upper wiring 2 of the uppermost layer in the step (j) after the gettering material 50 is formed in the space 5 in the step (i) of FIG. . Kiyabbingu layer 5 2, for example, be formed by forming a S i O _2. This film formation, for example, by low pressure CVD apparatus, a use gas as the S i H ₄ 0 ₂ (or _{N 0 2), 5;.} 1 ~ 1 4 of the flow rate of about 0 0 5-0 - 2 liters per minute, about the flow rate of O ₂ 0. 6 ~ 2 liters and per minute, about 1 3 0 the pressure in the reaction chamber P a, about 3 5 0 ° C or less 1 5 the substrate temperature 0 ° C or more.

In FIG. 15, after the upper wiring 2 is formed, the gettering material 50 is provided on the same layer as the upper wiring 2, but before the (a) step, the gettering material is provided. (I) to (II).

Further, a method for manufacturing the semiconductor device (seventh embodiment) shown in FIG. 14 will be described based on FIGS. The support 51 is similar to the formation process of the support 25 shown in FIGS. 6 and 7, and the first half of the steps (a) to (h) is the same as in FIGS. 6 and 7. is there. In FIG. 18, a (h-I-1) resist film 31a is applied and cured, and is patterned by (h-I-12) resist exposure to form a photo-resist mask 31. Next, (h-Π) gettering film 32 is formed. This formation is similar to the above-mentioned (a-Π) step. Since the gettering film 32 has an appropriate thickness, as shown in FIG. 19, the mask 31 is removed in the (h—) process. Next, the step of removing the sacrificial layer 22 is the same as the step (i) shown in FIG. 7, and as shown in FIG. 14, the gettering material is provided on the support 51 provided in the space 5. 50 are provided. Subsequently, as shown in the step (j), a caving layer 52 is formed in the same manner as the step (j) in FIG. 17 so as to cover the upper wiring 2 of the uppermost layer.

In the manufacturing method shown in FIGS. 18 and 19, the (h−I), (h−I), and the gettering material 50 are arranged at predetermined positions after the (h) step of forming the upper wiring 2. (h-Π) and (h — ΠΙ) processes are provided.

The gettering material disposing steps (I) to (m) may be performed before or after the formation of the upper wiring 2. Therefore, after the mask 27 required for cutting six metal pieces is removed in the step (g) shown in FIG. 7 and before forming the upper wiring 2, (g-I), (g-Π) and (g) g — ΙΠ) It may be provided as a process.

As shown in FIG. 4 or FIG. 5, the cabling layer 52 can also be formed in a space 5 that is continuous with the element isolation recess 10. Also in this case, the steps (I) to (IE) for forming the gettering layer 50 are inserted after the step (g) or the step (h), and finally, in the step (j), the cabbing layer 52 is formed. To form For example, when the gettering layer 50 is formed on the way, the (i-1) process in FIG. 10 is as shown in (i-1) in FIG. Subsequently, a cabling layer 52 is formed, and an airtight space 5 is formed as shown in (j) of FIG. Industrial applicability

As described above, the semiconductor device ′ and the method of manufacturing the same according to the present invention are suitable for miniaturization of an integrated circuit, and can stabilize the high-speed operation of the integrated circuit and extend the life of the semiconductor device.

Claims

The scope of the claims

1. In a semiconductor device provided on a silicon substrate on which a plurality of elements are provided so that at least two layers are provided above and below a wiring connecting the elements,

A pillar connected to the lower surface of the upper layer wiring and supporting the upper layer wiring is formed, and a space that is continuous from at least a part of the lower surface of the upper layer wiring is formed from a gap between the lower layer wirings. Characteristic semiconductor device.

2. The semiconductor device according to the item 1, wherein the pillar is an insulator.

3. The support includes a first support provided on the lower wiring and supporting the upper wiring, and a second support supporting the upper wiring at a portion on the silicon substrate without the lower wiring, 3. The semiconductor device according to claim 2, wherein at least one of the first posts has a metal for conduction.

4. The semiconductor device according to the item 1, wherein the support is a conductor.

5. The semiconductor device according to any one of items 1 to 4, wherein a concave portion for separating an element is formed on a substrate surface between the elements, and the space is continuous in the concave portion. .

6. The semiconductor device according to the above item 5, wherein an etching-resistant film is formed on an inner surface of the inter-element isolation recess.

7. The semiconductor device according to any one of Items 1 to 6, wherein a gettering material is provided in the space.

8. The semiconductor device according to claim 7, further comprising a cabling layer that covers the upper and lower wirings from above the uppermost wiring, and hermetically closes a space in which the gettering material is provided.

9. A method for manufacturing a semiconductor device in which wiring connecting the elements is provided on a silicon substrate on which a plurality of elements are provided so as to form at least two layers above and below, (a) forming the lower wiring on an interlayer insulating film provided on the silicon substrate;

(d) etching the sacrificial layer in the pillar formation region;

(θ) forming and burying an insulating film in the etched region to form a support;

(f) Forming a contact hole opening pattern mask for burying a metal for conducting the upper wiring to one or more layers below the lower wiring, and etching the pillar and the metal or sacrifice layer in the metal buried area Forming a contact hole by

(g) embedding a metal in the etched contact hole;

(h) forming the upper wiring layer;

A method for manufacturing a semiconductor device, comprising:

10. The method of manufacturing a semiconductor device according to the item 9, wherein the steps (g) and (h) are performed simultaneously.

11. A method for manufacturing a semiconductor device, comprising: a silicon substrate on which a plurality of elements are provided; wherein at least two layers are provided above and below wirings connecting the elements;

(a) forming the lower layer wiring on an interlayer insulating film provided on the silicon substrate; Forming a wire;

(b) A sacrificial layer is formed between the lower wirings and so as to cover the upper surface thereof.

(d) etching the sacrificial layer in the pillar formation region;

(Θ-1) a step of forming and embedding a metal in the etched region to form a conductive support;

(h) forming the upper wiring layer;

A method for manufacturing a semiconductor device, comprising:

12. The method for manufacturing a semiconductor device according to the item 11, wherein the step (e-1) and the step (h) are simultaneously performed.

1 3. After the above (i)

(j) a step of forming a cabling layer on the upper layer upper wiring so as to hermetically close the space.

13. The method for manufacturing a semiconductor device according to any one of the above items 9 to 12, comprising:

14. Between step (a) and step (b),

(a-1) A photoresist mask for forming a through hole for exposing a region for forming a device isolation recess of the silicon substrate in the interlayer insulating film is provided on the interlayer insulating film and the lower layer. A step of forming on the wiring by photolithography,

(a-2) The interlayer insulation in an area not covered by the photoresist mask Etching the edge film to form the through hole, exposing an element isolation recess forming region of the silicon substrate under the interlayer insulating film through the through hole;

(a-3) a step of removing the photo resist mask formed in the step (a-1)

14. The method for manufacturing a semiconductor device according to any one of the ninth to thirteenth aspects, wherein, is inserted.

15 5. Between step (a) and step (b),

(a-111) forming a photo-resist mask on the interlayer insulating film and the lower-layer wiring on the silicon substrate by photolithography to form a recess for element isolation;

(a-2-1) Etch the area not covered with the photoresist mask, penetrate the interlayer insulating film above the element isolation recess formation area, and furthermore, pass the silicon substrate immediately thereunder to a predetermined depth. Drilling down to form a recess for element isolation;

(a-3-1) a step of removing the photo resist mask formed in the step (a-1-1)

14. The method for manufacturing a semiconductor device according to any one of the above items 9 to 13, wherein a semiconductor device is inserted.

16. The method of manufacturing a semiconductor device according to any one of the above items 9 to 15, wherein the sacrificial layer is a silicon layer.

7. The method of manufacturing a semiconductor device according to any one of the above items 9 to 15, wherein the sacrificial layer is a resist layer.

18. Before or after the step (a),

(I) a step of forming a mask for forming a gettering material, (Iii) forming a gettering material film, and

(m) removing the gettering material forming mask to obtain a gettering material layer;

18. The method for manufacturing a semiconductor device according to any one of the above items 9 to 17, wherein a semiconductor device is inserted.

1 9. Before or after step (h),

(I) a step of forming a mask for forming a gettering material,

(Iii) forming a gettering material film, and

(Ii) removing the gettering material forming mask to obtain a gettering material layer;

19. The method for manufacturing a semiconductor device according to any one of the above items 9 to 18, wherein a semiconductor device is inserted.