WO2001095376A3 - Methods for forming rough ruthenium-containing layers and structures/methods using same - Google Patents

Methods for forming rough ruthenium-containing layers and structures/methods using same Download PDF

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Publication number
WO2001095376A3
WO2001095376A3 PCT/US2001/040867 US0140867W WO0195376A3 WO 2001095376 A3 WO2001095376 A3 WO 2001095376A3 US 0140867 W US0140867 W US 0140867W WO 0195376 A3 WO0195376 A3 WO 0195376A3
Authority
WO
WIPO (PCT)
Prior art keywords
ruthenium
methods
rough ruthenium
rough
structures
Prior art date
Application number
PCT/US2001/040867
Other languages
French (fr)
Other versions
WO2001095376A2 (en
Inventor
Garo Derderian
Vishnu K Agarwal
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to EP01944651A priority Critical patent/EP1292992A2/en
Priority to AU2001267039A priority patent/AU2001267039A1/en
Priority to KR1020027016735A priority patent/KR100644454B1/en
Priority to JP2002502819A priority patent/JP2003535978A/en
Publication of WO2001095376A2 publication Critical patent/WO2001095376A2/en
Publication of WO2001095376A3 publication Critical patent/WO2001095376A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for forming a rough ruthenium-containing layer on the surface of a substrate assembly includes providing a ruthenium-containing precursor into the reaction chamber. A rough ruthenium layer may be deposited on the surface of the substrate assembly at a rate of about 100 Å/minute to about 500 Å/minute using the ruthenium-containing precursor. Further, a rough ruthenium oxide layer may be formed by providing a ruthenium-containing precursor and an oxygen-containing precursor into the reaction chamber to deposit the rough ruthenium oxide layer on the surface of the substrate assembly at a rate of about 100 Å/minute to about 1200 Å/minute. An anneal of the layers may be performed to further increase the roughness. In addition, conductive structures including a rough ruthenium layer or a rough ruthenium oxide layer are provided. Such layers may be used in conjunction with non-rough ruthenium and/or non-rough ruthenium oxide layers to form conductive structures. For example, such structures may be part of a capacitor structure, e.g., bottom electrode of a capacitor.
PCT/US2001/040867 2000-06-08 2001-06-07 Methods for forming rough ruthenium-containing layers and structures/methods using same WO2001095376A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP01944651A EP1292992A2 (en) 2000-06-08 2001-06-07 Methods for forming rough ruthenium-containing layers and structures/methods using same
AU2001267039A AU2001267039A1 (en) 2000-06-08 2001-06-07 Methods for forming rough ruthenium-containing layers and structures/methods using same
KR1020027016735A KR100644454B1 (en) 2000-06-08 2001-06-07 Methods for forming rough ruthenium-containing layers and structures/methods using same
JP2002502819A JP2003535978A (en) 2000-06-08 2001-06-07 Method of forming coarse ruthenium-containing layer, structure using coarse ruthenium-containing layer, and method of using coarse ruthenium-containing layer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/589,849 2000-06-08
US09/589,849 US6429127B1 (en) 2000-06-08 2000-06-08 Methods for forming rough ruthenium-containing layers and structures/methods using same

Publications (2)

Publication Number Publication Date
WO2001095376A2 WO2001095376A2 (en) 2001-12-13
WO2001095376A3 true WO2001095376A3 (en) 2002-06-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/040867 WO2001095376A2 (en) 2000-06-08 2001-06-07 Methods for forming rough ruthenium-containing layers and structures/methods using same

Country Status (6)

Country Link
US (4) US6429127B1 (en)
EP (1) EP1292992A2 (en)
JP (1) JP2003535978A (en)
KR (1) KR100644454B1 (en)
AU (1) AU2001267039A1 (en)
WO (1) WO2001095376A2 (en)

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Also Published As

Publication number Publication date
US20020058415A1 (en) 2002-05-16
AU2001267039A1 (en) 2001-12-17
KR100644454B1 (en) 2006-11-10
JP2003535978A (en) 2003-12-02
US20020058414A1 (en) 2002-05-16
WO2001095376A2 (en) 2001-12-13
US6897160B2 (en) 2005-05-24
EP1292992A2 (en) 2003-03-19
US6429127B1 (en) 2002-08-06
US20050208741A1 (en) 2005-09-22
KR20030010674A (en) 2003-02-05
US6784504B2 (en) 2004-08-31
US7144810B2 (en) 2006-12-05

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