WO2001093499A1

WO2001093499A1 - Non intrusive self test capability in the utopia level two bus

Info

Publication number: WO2001093499A1
Application number: PCT/IB2001/000950
Authority: WO
Inventors: Jacob Fainguelernt
Original assignee: Adc Telecommunications Israel Ltd.
Priority date: 2000-05-31
Filing date: 2001-05-30
Publication date: 2001-12-06
Also published as: WO2001093499A8; AU2001260529A1

Abstract

Systems and methods are provided for non intrusive self test capability in the UTOPIA level 2 bus within the ATM switch/multiplexer architecture. These systems and methods make use of the characteristics of ATM transport and the UTOPIA level 2 bus interface. The system includes an ATM switch/multiplexer architecture having an ATM layer device and a number of physical layer devices. A bus couples the ATM layer device to the number of physical layer devices. A self test circuit is coupled to the bus which is adapted to send received ATM cells back to the common layer circuit pack in order to perform a self test function without requiring additional wires or bandwidth.

Description

Non Intrusive Self Test Capability in the Utopia Level Two Bus

Technical Field of the Invention The present invention relates generally to the field of telecommunications and, in particular, to systems and methods for non intrusive self test capability in the UTOPIA level Two bus.

Background Asynchronous Transfer Mode (ATM) is the transfer mode of choice for broadband integrated services digital networks (B-ISDN). B-ISDNs are envisioned to be the communication framework for integrating multiple services as video, audio and data. Originally each one of the services is delivered over a dedicated network and its infrastructure. The use of ATM enables these services to be integrated in a single unified network deployed over the existing infrastructures. The ATM technology is based on transferring the various kinds of data in small packets of a fixed size, called cells. The small, constant cell size allows ATM equipment to transmit video, audio, and computer data over the same network, and assure that no single type of data hogs the line. ATM switches and multiplexers are necessary for routing the cells to their appropriate destination.

Figure 1 shows the general architecture of an ATM switch/multiplexer 100. This kind of equipment is composed of two basic types of functional blocks; the ATM common module 101 and the physical ports 103-1, 103-2, . . ., 103-N. The ATM common module 101 routes cells between the various physical ports, and performs signaling functions. The physical ports 103-1, 103-2, . . ., 103-N convert signals from the physical layer into ATM cells and vice-versa. Ports 103-1, 103-2, . . ., 103-N perform functions of the ATM physical layer (PHY), and the ATM common module 101 performs functions of the ATM layer and the ATM signaling adaptation layer (SAAL). As shown in Figure 2, a standard bus 202, defined by the ATM Forum as the

Universal Test & Physical Operations Interface for ATM (UTOPIA), provides the interface between the physical layer and the ATM layer. The UTOPIA level 2 version enables a "multi-physical" configuration where a single ATM layer device 201 (UTOPIA master) can be connected through this bus 202 to multiple physical layer devices 203-1, 203-2, . . ., 203-N (UTOPIA slaves). Prior art Figure 3 illustrates an ATM system 300 in which the ATM and

SAAL functionality is implemented in a common pack 301 that is connected to multiple interface packs 303-1, 303-2, . . ., 303-N, each one having the physical layer functionality. The data from the common pack to the interface packs and vice- versa, is transported through the system backplane. Because of its physical limitations, the UTOPIA level 2 bus cannot be implemented in a backplane. In this case the UTOPIA bus in the common pack 302, and the UTOPIA buses in the interface packs, shown generally as 305, are interconnected through special drivers (in both packs), e.g. Driver 1, Driver 2, . . ., Driver N..

ATM systems are required to provide self-testing capability. The UTOPIA level 2 bus supports an embedded parity check, which is not sufficient for and end to end internal system self-test. This test demands, instead, the implementation of internal loops. The straightforward implementation of a loopback consists on operating one of the physical ports in a loopback mode. This implementation is intrusive since during the test the port is halted. In other words, the port being tested has to be taken out of service while the self test is perfoπned.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved systems and methods for providing non intrusive self test capability in the UTOPIA level 2 bus within the ATM switch/multiplexer architecture. That is, it would be desirable to continue live communication over the network and test various components simultaneously.

Summary The above mentioned problems with self test capability in the UTOPIA level 2 bus within the ATM switch/multiplexer architecture and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Systems and methods are provided for non intrusive self test capability in the UTOPIA level 2 bus within the ATM switch/multiplexer architecture. These systems and methods make use of the characteristics of ATM transport and the UTOPIA level 2 bus interface.

In one embodiment, an ATM switch/multiplexer system for non-intrusive self-test capability in a UTOPIA level 2 bus is provided. The system includes an ATM layer device. A number of physical layer devices are included. A bus couples the ATM layer device to the number of physical layer devices. And, a dedicated self test circuit couples to the bus. According to the teachings of the present invention, the dedicated self test circuit is adapted to loop back cells from the ATM layer device in a self test function. That is the self test circuit is adapted to send received ATM cells back to the ATM layer device, through a dedicated virtual circuit, in order to perform a self test function without requiring additional wires or bandwidth. In one embodiment, the ATM layer device includes a UTOPIA master and the physical layer devices are UTOPIA slaves. The number of physical layer devices include physical ports adapted for converting signals from a physical layer into ATM cells and converting ATM cells into signals for the physical layer. The dedicated self test circuit has a lower priority between the ATM device layer number of physical devices in order to perform a non intrusive self test function.

Brief Description of the Drawings Figure 1 is a block diagram that illustrates a conventional ATM switch/multiplexer circuit.

Figure 2 is another representation of a conventional ATM switch/multiplexer circuit.

Figure 3 is another representation of a conventional ATM switch/multiplexer circuit.

Figure 4 is a block circuit diagram that illustrates an embodiment of an ATM switch/multiplexer system for non-intrusive self-test capability in a UTOPIA level 2 bus according to the teachings of the present invention.

Figure 5 is a block circuit diagram that illustrates another embodiment for an ATM switch/multiplexer system according to the teachings of the present invention. Figure 6 is a block circuit diagram that illustrates another embodiment for an ATM switch/multiplexer system according to the teachings of the present invention.

Detailed Description The following detailed description refers to the accompanying drawings which form a part of the specification. The drawings show, and the detailed description describes, by way of illustration specific illustrative embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be used and logical, mechanical and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense.

Figure 4 is a block circuit diagram that illustrates an ATM switch/multiplexer system 400 for non-intrusive self-test capability in a UTOPIA level 2 bus, according to the teachings of the present invention. As shown in Figure 4, the ATM switch/multiplexer system includes an ATM layer device 401. A number of physical layer devices 403-1, 403-2, . . ., 403-N are included. A bus 402 couples the ATM layer device 401 to the number of physical layer devices 403-1, 403-2, . . ., 403-N. In one embodiment, the bus 402 includes a UTOPIA level 2 bus 402. A dedicated self test circuit 405 is coupled to the bus 402. The dedicated self test circuit 405 includes external logic either in the form of a programmable device or discrete components which is coupled to the bus 402. Self test circuit 405 communicates with the ATM layer device 401 over a dedicated virtual connection. In one embodiment, the ATM layer device 401 includes a UTOPIA master and the number of physical layer devices 403-1, 403-2, . . ., 403-N are UTOPIA slaves. In one embodiment, the UTOPIA master is adapted to perform ATM and ATM signaling adaptation layer (SAAL) functions. In one embodiment, the ATM layer device 401 and the number of physical layer devices 403-1, 403-2, . . ., 403-N are located in a single circuit pack. The number of physical layer devices 403-1, 403-2, . . ., 403-N include physical ports adapted for converting signals from a physical layer into ATM cells and converting ATM cells into signals for the physical layer. The ATM layer device 401 includes a common module or pack adapted for routing ATM cells between the number of physical layer devices.

In operation, system 400 provides a non-intrusive self-test functionality. The dedicated virtual connection 405 is adapted to send received ATM cells back to the ATM layer device 401 in order to perform a self test function. If the ATM cells returned to the ATM layer device 401 do not match those which were sent out or the cells are not received, the ATM layer device 401 recognizes that there is a problem with system 400. In the present invention, the self test circuit 405 actually imitates a given physical layer device address 403-1, 403-2, . . ., 403-N. The diagnostics of the self test function are performed in the ATM layer device 401. And, the dedicated self test circuit 405 through its dedicated virtual connection has a lower priority between the common pack and the number of physical devices in order to perform a non intrusive self test function without requiring additional wires or bandwidth.

Figure 5 is a block circuit diagram that illustrates another embodiment for an ATM switch/multiplexer system 500, according to the teachings of the present invention. The ATM switch/multiplexer system 500, similarly provides for non- intrusive self-test capability in a Utopia level 2 bus. As shown in Figure 5, the system 500 includes an ATM layer device 501, or common layer circuit pack 501, and a number of interface layer circuit packs 503-1, 503-2, . . ., 503-N. The common layer circuit pack 501 includes an internal bus 502. In one embodiment, the internal bus 502 includes a UTOPIA level 2 bus. The number of interface layer circuit packs 503-1, 503-2, . . ., 503-N include a number of ports, shown as Port #1, Port #2, . . ., Port #N. Each port has includes an internal bus, shown generally as 505, coupling between a driver, 511-1, 511-2, . . ., 511-N, and a physical layer device, e.g. 507-1, 507-2, . . ., 507-N. In one embodiment the bus includes a UTOPIA level 2 bus 505.

As shown in Figure 5, each of the number of ports, Port #1, Port #2, . . ., Port #N, includes a dedicated self test circuit 509-1, 509-2, . . ., 509-N. A number of drivers 511-1, 511-2, . . ., 511-N interconnect, or couple, the buses 505 in the number of ports, Port #1 , Port #2, . . ., Port #N, to the bus 502 in the ATM layer device 501, or common layer circuit pack 501. Each dedicated self test circuit 509- 1, 509-2, . . ., 509-N communicates with common layer circuit pack 501 over a dedicated virtual connection. The common layer circuit pack is adapted to perform the functions of the ATM layer and the SAAL. In one embodiment, each dedicated self test circuit 509-1, 509-2, . . ., 509-N includes a programmable device.

According to the teachings of the present invention, the number of physical ports, Port #1, Port #2, . . ., Port #N, including the number of physical layer devices, are adapted for converting signals from the physical layer devices, e.g. 507-1, 507-2, . . ., 507 -N, into ATM cells and converting ATM cells into signals for the physical layer devices 507-1, 507-2, . . ., 507-N.

According to the teachings of the present invention, each dedicated self test circuit 509-1, 509-2, . . ., 509-N coupled to the bus 505 in the number of interface layer circuit packs 503-1, 503-2, . . ., 503-N is generic and independent from a functionality for the number of drivers 511-1, 511-2, . . ., 511-N. As described above in connection with Figure 4, each dedicated virtual connection 509-1, 509-2, . . ., 509-N is adapted to send received ATM cells back to the common layer circuit pack 501 in order to perform a self test function without requiring additional wires or bandwidth. Thus, in operation, system 500 provides a non-intrusive self-test functionality. Each dedicated self-test circuit 509-1, 509-2, . . ., 509-Ν through its dedicated virtual connection has a lower priority between the common layer circuit pack 501 and the physical devices 507-1, 507-2, . . ., 507-N in the number of ports Port #1, Port #2, . . ., Port #N in order to perform a non intrusive self test function. Figure 6 is a block circuit diagram that illustrates another embodiment for an ATM switch/multiplexer system 600, according to the teachings of the present invention. The ATM switch/multiplexer system embodiment 600 shown in Figure 6, similarly provides for non-intrusive self-test capability in a Utopia level 2 bus. In the embodiment of Figure 6, each of the number of ports Port #1, Port #2, . . ., Port #N includes programmable device such as an Application Specific Integrated Circuit (ASIC) or a field programmable gate array (FPGA). According to the teachings for this embodiment, the physical layer devices 607-1, 607-2, . . ., 607 -N are included as part of the ASIC or the FPGA. Further, according to the embodiment shown in Figure 6, each dedicated self test circuit 609-1, 609-2, . . ., 609-N is a functional block of the ASIC or FPGA. As was described in detail in connection with Figure 5, each dedicated self test circuit 609-1, 609-2, . . ., 609-N is coupled to the internal bus 605 within the ASIC or FPGA to perform the self test function in conjunction with ATM layer device 601.

Conclusion Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Systems and methods have been illustrated for providing non intrusive self test capability in the UTOPIA level 2 bus within an ATM switch/multiplexer architecture. These systems and methods make use of the characteristics of ATM transport and the UTOPIA level 2 bus interface.

Claims

What is claimed is:

1. An ATM circuit, the circuit comprising: an ATM layer device; a number of physical layer devices; a UTOPIA level 2 bus coupling the ATM layer device to the number of physical layer devices; and a dedicated self-test circuit coupled to the UTOPIA level 2 bus, the dedicated self test circuit being adapted to loop back cells from the ATM layer device in a self est mode.

2. The circuit of claim 1 , wherein ATM layer device includes a UTOPIA master and the number of physical layer devices are UTOPIA slaves.

3. The circuit of claim 1 , wherein the number of physical layer devices include physical ports adapted for converting signals from a physical layer into ATM cells and converting ATM cells into signals for the physical layer.

4. The circuit of claim 1 , wherein ATM layer device includes a common module or pack adapted for routing ATM cells between the number of physical layer devices.

5. The circuit of claim 1, wherein the dedicated self test circuit communicates with the ATM layer device over a dedicated virtual connection that has a lower priority than virtual connections between the ATM layer device and the number of physical devices in order to perform a non intrusive self test function.

6. An ATM circuit, comprising: an ATM layer device; a number of physical layer devices; a UTOPIA level 2 bus coupling the ATM layer device to the number of physical layer devices; and a self test circuit coupled to the UTOPIA level 2 bus, wherein the self test circuit is adapted to send received ATM cells back to the ATM layer device in order to perform a self test function without requiring additional wires or bandwidth.

7. The circuit of claim 6, wherein ATM layer device includes a UTOPIA master and the number of physical layer devices are UTOPIA slaves, and wherein the ATM and physical layer devices are included a single circuit pack.

8. The circuit of claim 6, wherein the self test circuit includes a programmable device.

9. The circuit of claim 6, wherein the number of physical layer devices include physical ports adapted for converting signals from a physical layer into ATM cells and converting ATM cells into signals for the physical layer.

10. The circuit of claim 6, wherein ATM layer device includes a common module or pack adapted for routing ATM cells between the number of physical layer devices.

11. The circuit of claim 6, wherein the dedicated self test circuit communicates with the ATM layer device over a dedicated virtual connection that has a lower priority than virtual connections between the ATM layer device and the number of physical devices in order to perform a non intrusive self test function.

12. An ATM circuit, comprising: a common layer circuit pack having a UTOPIA level 2 bus; a number of interface layer circuit packs including a number of ports, each port having a UTOPIA level 2 bus and including a self-test circuit coupled to the UTOPIA level 2 bus of the interface layer circuit pack; and a number of drivers interconnecting the UTOPIA level 2 bus in the common circuit pack and the UTOPIA level 2 bus in the interface layer circuit pack.

13. The circuit of claim 12, wherein the common layer circuit pack is adapted to perform the functions of an ATM layer and an SAAL layer.

14. The circuit of claim 12, wherein each self test circuit coupled to the UTOPIA level 2 bus in the number of interface layer circuit packs is generic.

15. The circuit of claim 12, wherein each of the number of ports includes a physical layer device.

16. The circuit of claim 12, wherein each of the number of ports is adapted for converting signals from a physical layer into ATM cells and converting ATM cells into signals for the physical layer.

17. The circuit of claim 12, wherein each self test circuit is adapted to send received ATM cells back to the common layer circuit pack in order to perform a self test function without requiring additional wires or bandwidth.

18. The circuit of claim 16, wherein the dedicated self test circuit communicates with the ATM layer device over a dedicated virtual connection that has a lower priority than virtual connections between the ATM layer device and the number of physical devices in order to perform a non intrusive self test function.

19. The circuit of claim 12, wherein each of the number of ports includes one of an ASIC or a FPGA.

20. The circuit of claim 18, wherein each self test circuit is a functional block of one of the ASIC or the FPGA.

21. A method for performing a non intrusive self test in an ATM circuit, the method comprising: coupling an ATM layer device to a number of physical layer devices using a UTOPIA level 2 bus; and coupling a dedicated self test circuit to the UTOPIA level 2 bus.

22. The method of claim 21 , wherein coupling an ATM layer device to a number of physical layer devices using a UTOPIA level 2 bus includes wherein coupling the ATM layer device to a number of physical layer devices in a single circuit pack.

23. The method of claim 21 , wherein coupling a self test circuit to the UTOPIA level 2 bus includes coupling one of a programmable device and discrete components to the number of physical layer devices. .

24. The method of claim 21 , wherein coupling an ATM layer device to a number of physical layer devices using a UTOPIA level 2 bus includes coupling a number of physical layer devices which include one of an ASIC or an FPGA as a physical port.

25. The method of claim 24, wherein coupling a dedicated self test circuit to the bus includes coupling the dedicated self test circuit as a functional block of the one of the ASIC or the FPGA.

26. A method for self-testing an ATM circuit, the method comprising: generating cells at an ATM layer device; transmitting the cells to a UTOPIA level 2 bus; and when the ATM circuit functions properly, re-transmitting the cells back to the ATM layer device from a self test circuit associated with the UTOPIA level 2 bus.