WO2001090915A3 - Processor array and parallel data processing methods - Google Patents

Processor array and parallel data processing methods Download PDF

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Publication number
WO2001090915A3
WO2001090915A3 PCT/CA2001/000712 CA0100712W WO0190915A3 WO 2001090915 A3 WO2001090915 A3 WO 2001090915A3 CA 0100712 W CA0100712 W CA 0100712W WO 0190915 A3 WO0190915 A3 WO 0190915A3
Authority
WO
WIPO (PCT)
Prior art keywords
data processing
processor elements
parallel data
processing methods
array
Prior art date
Application number
PCT/CA2001/000712
Other languages
French (fr)
Other versions
WO2001090915A2 (en
Inventor
Jeremy Wilson
Jayson D Strayer
Original Assignee
Gazelle Technology Corp
Jeremy Wilson
Jayson D Strayer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gazelle Technology Corp, Jeremy Wilson, Jayson D Strayer filed Critical Gazelle Technology Corp
Priority to AU2001261944A priority Critical patent/AU2001261944A1/en
Publication of WO2001090915A2 publication Critical patent/WO2001090915A2/en
Publication of WO2001090915A3 publication Critical patent/WO2001090915A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Abstract

An array of processor elements has multiple instruction streams and multiple data streams broadcast to all of the processor elements. The processor elements are each connected to multiple neighbouring processor elements within a cruciate neighbourhood. The architecture is suitable for use in fine-grained applications. The array may have a processor element for each pixel of an image. The array is preferably provided on a single integrated circuit having 10,000 or more processor elements.
PCT/CA2001/000712 2000-05-22 2001-05-22 Processor array and parallel data processing methods WO2001090915A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001261944A AU2001261944A1 (en) 2000-05-22 2001-05-22 Processor array and parallel data processing methods

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/576,871 2000-05-22
US09/576,871 US6728862B1 (en) 2000-05-22 2000-05-22 Processor array and parallel data processing methods

Publications (2)

Publication Number Publication Date
WO2001090915A2 WO2001090915A2 (en) 2001-11-29
WO2001090915A3 true WO2001090915A3 (en) 2003-08-14

Family

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Family Applications (1)

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PCT/CA2001/000712 WO2001090915A2 (en) 2000-05-22 2001-05-22 Processor array and parallel data processing methods

Country Status (3)

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US (1) US6728862B1 (en)
AU (1) AU2001261944A1 (en)
WO (1) WO2001090915A2 (en)

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6895520B1 (en) 2001-03-02 2005-05-17 Advanced Micro Devices, Inc. Performance and power optimization via block oriented performance measurement and control
US20020178207A1 (en) * 2001-03-22 2002-11-28 Mcneil Donald H. Ultra-modular processor in lattice topology
US6970509B2 (en) * 2001-07-31 2005-11-29 Wis Technologies, Inc. Cell array and method of multiresolution motion estimation and compensation
US7142251B2 (en) * 2001-07-31 2006-11-28 Micronas Usa, Inc. Video input processor in multi-format video compression system
US7085320B2 (en) * 2001-07-31 2006-08-01 Wis Technologies, Inc. Multiple format video compression
US20050207663A1 (en) * 2001-07-31 2005-09-22 Weimin Zeng Searching method and system for best matching motion vector
US7219173B2 (en) * 2001-07-31 2007-05-15 Micronas Usa, Inc. System for video processing control and scheduling wherein commands are unaffected by signal interrupts and schedule commands are transmitted at precise time
US7035332B2 (en) * 2001-07-31 2006-04-25 Wis Technologies, Inc. DCT/IDCT with minimum multiplication
US7184101B2 (en) * 2001-07-31 2007-02-27 Micronas Usa, Inc. Address generation for video processing
US6996702B2 (en) * 2001-07-31 2006-02-07 Wis Technologies, Inc. Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention
US6981073B2 (en) * 2001-07-31 2005-12-27 Wis Technologies, Inc. Multiple channel data bus control for video processing
DE10158784B4 (en) * 2001-11-30 2006-03-16 Infineon Technologies Ag A method for determining a distance of processor units to at least one reference position in a processor arrangement and processor arrangement
EP1449110A2 (en) * 2001-11-30 2004-08-25 Infineon Technologies AG Method for determination of a separation from processor units to at least one reference position in a processor arrangement and processor arrangement
US7159059B2 (en) * 2002-03-01 2007-01-02 Mcneil Donald H Ultra-modular processor in lattice topology
GB2395299B (en) * 2002-09-17 2006-06-21 Micron Technology Inc Control of processing elements in parallel processors
US20060001669A1 (en) * 2002-12-02 2006-01-05 Sehat Sutardja Self-reparable semiconductor and method thereof
US7673118B2 (en) 2003-02-12 2010-03-02 Swarztrauber Paul N System and method for vector-parallel multiprocessor communication
US7366352B2 (en) * 2003-03-20 2008-04-29 International Business Machines Corporation Method and apparatus for performing fast closest match in pattern recognition
GB2399899B (en) 2003-03-27 2005-06-22 Micron Technology Inc Active memory command engine and method
GB2400195B (en) * 2003-03-31 2005-06-29 Micron Technology Inc Active memory processing array topography and method
US7596678B2 (en) * 2003-04-23 2009-09-29 Micron Technology, Inc. Method of shifting data along diagonals in a group of processing elements to transpose the data
US7913062B2 (en) * 2003-04-23 2011-03-22 Micron Technology, Inc. Method of rotating data in a plurality of processing elements
US7676648B2 (en) * 2003-04-23 2010-03-09 Micron Technology, Inc. Method for manipulating data in a group of processing elements to perform a reflection of the data
US7581080B2 (en) * 2003-04-23 2009-08-25 Micron Technology, Inc. Method for manipulating data in a group of processing elements according to locally maintained counts
EP1643356B1 (en) * 2003-05-23 2010-01-06 Nippon Telegraph and Telephone Corporation Parallel processing device and parallel processing method
US7983835B2 (en) 2004-11-03 2011-07-19 Lagassey Paul J Modular intelligent transportation system
CN101427264A (en) * 2004-04-08 2009-05-06 硅奥普迪思公司 Method and apparatus for high density storage and handling of bit-plane data
CN101432760A (en) 2004-08-31 2009-05-13 硅奥普迪思公司 Method and apparatus for management of bit plane resources
US8024549B2 (en) * 2005-03-04 2011-09-20 Mtekvision Co., Ltd. Two-dimensional processor array of processing elements
HUP0500482A2 (en) * 2005-05-11 2006-12-28 Mta Szamitastech Autom Kutato System and method for sensing and processing electromagnetic signals
GB0519597D0 (en) * 2005-09-26 2005-11-02 Imagination Tech Ltd Scalable multi-threaded media processing architecture
US9563433B1 (en) * 2006-09-01 2017-02-07 Allsearch Semi Llc System and method for class-based execution of an instruction broadcasted to an array of processing elements
US20080141013A1 (en) * 2006-10-25 2008-06-12 On Demand Microelectronics Digital processor with control means for the execution of nested loops
US20080307206A1 (en) * 2006-11-28 2008-12-11 On Demand Microelectronics Method and apparatus to efficiently evaluate monotonicity
US7827515B2 (en) * 2007-03-15 2010-11-02 Oracle America, Inc. Package designs for fully functional and partially functional chips
US8078829B2 (en) * 2007-12-12 2011-12-13 Itt Manufacturing Enterprises, Inc. Scaleable array of micro-engines for waveform processing
US9003274B2 (en) 2007-12-21 2015-04-07 International Business Machines Corporation Scheduling start-up and shut-down of mainframe applications using topographical relationships
US8755515B1 (en) 2008-09-29 2014-06-17 Wai Wu Parallel signal processing system and method
US9946665B2 (en) 2011-05-13 2018-04-17 Melange Systems Private Limited Fetch less instruction processing (FLIP) computer architecture for central processing units (CPU)
US9329834B2 (en) 2012-01-10 2016-05-03 Intel Corporation Intelligent parametric scratchap memory architecture
FR3028070B1 (en) * 2014-11-04 2017-02-24 Commissariat Energie Atomique METHOD AND DEVICE FOR CONFIGURABLE ARCHITECTURE WITH LARGE GRAINS TO COMPLETELY EXECUTE AN APPLICATION CODE
US9749548B2 (en) 2015-01-22 2017-08-29 Google Inc. Virtual linebuffers for image signal processors
WO2016163421A1 (en) * 2015-04-08 2016-10-13 国立大学法人奈良先端科学技術大学院大学 Data processing device
US9772852B2 (en) 2015-04-23 2017-09-26 Google Inc. Energy efficient processor core architecture for image processor
US9769356B2 (en) 2015-04-23 2017-09-19 Google Inc. Two dimensional shift array for image processor
US10291813B2 (en) 2015-04-23 2019-05-14 Google Llc Sheet generator for image processor
US9785423B2 (en) 2015-04-23 2017-10-10 Google Inc. Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
US9965824B2 (en) 2015-04-23 2018-05-08 Google Llc Architecture for high performance, power efficient, programmable image processing
US10095479B2 (en) 2015-04-23 2018-10-09 Google Llc Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure
US9756268B2 (en) 2015-04-23 2017-09-05 Google Inc. Line buffer unit for image processor
US10313641B2 (en) * 2015-12-04 2019-06-04 Google Llc Shift register with reduced wiring complexity
US9830150B2 (en) 2015-12-04 2017-11-28 Google Llc Multi-functional execution lane for image processor
US10387988B2 (en) 2016-02-26 2019-08-20 Google Llc Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
US10204396B2 (en) 2016-02-26 2019-02-12 Google Llc Compiler managed memory for image processor
US10380969B2 (en) 2016-02-28 2019-08-13 Google Llc Macro I/O unit for image processor
US20180005346A1 (en) 2016-07-01 2018-01-04 Google Inc. Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register
US20180005059A1 (en) 2016-07-01 2018-01-04 Google Inc. Statistics Operations On Two Dimensional Image Processor
US20180007302A1 (en) 2016-07-01 2018-01-04 Google Inc. Block Operations For An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register
US10546211B2 (en) 2016-07-01 2020-01-28 Google Llc Convolutional neural network on programmable two dimensional image processor
US11277455B2 (en) 2018-06-07 2022-03-15 Mellanox Technologies, Ltd. Streaming system
US10831702B2 (en) * 2018-09-20 2020-11-10 Ceva D.S.P. Ltd. Efficient utilization of systolic arrays in computational processing
US20200106828A1 (en) * 2018-10-02 2020-04-02 Mellanox Technologies, Ltd. Parallel Computation Network Device
US10831507B2 (en) 2018-11-21 2020-11-10 SambaNova Systems, Inc. Configuration load of a reconfigurable data processor
US11625393B2 (en) 2019-02-19 2023-04-11 Mellanox Technologies, Ltd. High performance computing system
EP3699770A1 (en) 2019-02-25 2020-08-26 Mellanox Technologies TLV Ltd. Collective communication system and methods
US11750699B2 (en) 2020-01-15 2023-09-05 Mellanox Technologies, Ltd. Small message aggregation
US11252027B2 (en) 2020-01-23 2022-02-15 Mellanox Technologies, Ltd. Network element supporting flexible data reduction operations
US11876885B2 (en) 2020-07-02 2024-01-16 Mellanox Technologies, Ltd. Clock queue with arming and/or self-arming features
US11556378B2 (en) 2020-12-14 2023-01-17 Mellanox Technologies, Ltd. Offloading execution of a multi-task parameter-dependent operation to a network device
US11556494B1 (en) * 2021-07-16 2023-01-17 SambaNova Systems, Inc. Defect repair for a reconfigurable data processor for homogeneous subarrays
US11327771B1 (en) 2021-07-16 2022-05-10 SambaNova Systems, Inc. Defect repair circuits for a reconfigurable data processor
US11409540B1 (en) 2021-07-16 2022-08-09 SambaNova Systems, Inc. Routing circuits for defect repair for a reconfigurable data processor
US11922237B1 (en) 2022-09-12 2024-03-05 Mellanox Technologies, Ltd. Single-step collective operations

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996008778A1 (en) * 1994-09-13 1996-03-21 Lockheed Martin Corporation Parallel data processor
EP0726529A2 (en) * 1994-12-29 1996-08-14 International Business Machines Corporation Array processor topology reconfiguration system and method
US5724535A (en) * 1994-09-15 1998-03-03 U.S. Philips Corporation Data processing system

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459846A (en) 1988-12-02 1995-10-17 Hyatt; Gilbert P. Computer architecture system having an imporved memory
US4314349A (en) 1979-12-31 1982-02-02 Goodyear Aerospace Corporation Processing element for parallel array processors
US4827445A (en) 1982-02-18 1989-05-02 University Of North Carolina Image buffer having logic-enhanced pixel memory cells and method for setting values therein
US5584032A (en) 1984-10-17 1996-12-10 Hyatt; Gilbert P. Kernel processor system
US4805091A (en) 1985-06-04 1989-02-14 Thinking Machines Corporation Method and apparatus for interconnecting processors in a hyper-dimensional array
US5045995A (en) 1985-06-24 1991-09-03 Vicom Systems, Inc. Selective operation of processing elements in a single instruction multiple data stream (SIMD) computer system
US4722084A (en) 1985-10-02 1988-01-26 Itt Corporation Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits
US4751656A (en) 1986-03-10 1988-06-14 International Business Machines Corporation Method for choosing replacement lines in a two dimensionally redundant array
US5367208A (en) 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
US4967392A (en) 1988-07-27 1990-10-30 Alliant Computer Systems Corporation Drawing processor for computer graphic system using a plurality of parallel processors which each handle a group of display screen scanlines
US5072371A (en) 1989-03-01 1991-12-10 The United States Of America As Represented By The United States Department Of Energy Method for simultaneous overlapped communications between neighboring processors in a multiple
US6038584A (en) 1989-11-17 2000-03-14 Texas Instruments Incorporated Synchronized MIMD multi-processing system and method of operation
US5212777A (en) 1989-11-17 1993-05-18 Texas Instruments Incorporated Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation
US5280474A (en) 1990-01-05 1994-01-18 Maspar Computer Corporation Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays
US5546343A (en) 1990-10-18 1996-08-13 Elliott; Duncan G. Method and apparatus for a single instruction operating multiple processors on a memory chip
US5625836A (en) 1990-11-13 1997-04-29 International Business Machines Corporation SIMD/MIMD processing memory element (PME)
US5291431A (en) 1991-06-03 1994-03-01 General Electric Company Array multiplier adapted for tiled layout by silicon compiler
US5404550A (en) 1991-07-25 1995-04-04 Tandem Computers Incorporated Method and apparatus for executing tasks by following a linked list of memory packets
JP2647327B2 (en) 1992-04-06 1997-08-27 インターナショナル・ビジネス・マシーンズ・コーポレイション Massively parallel computing system equipment
TW390446U (en) * 1992-10-01 2000-05-11 Hudson Soft Co Ltd Information processing system
US5388206A (en) 1992-11-13 1995-02-07 The University Of North Carolina Architecture and apparatus for image generation
GB2273377A (en) 1992-12-11 1994-06-15 Hughes Aircraft Co Multiple masks for array processors
DE69519426T2 (en) 1994-03-22 2001-06-21 Hyperchip Inc Cell-based fault-tolerant architecture with advantageous use of the unallocated redundant cells
US5590356A (en) 1994-08-23 1996-12-31 Massachusetts Institute Of Technology Mesh parallel computer architecture apparatus and associated methods
US5606707A (en) 1994-09-30 1997-02-25 Martin Marietta Corporation Real-time image processor
US6128720A (en) * 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
US5649135A (en) 1995-01-17 1997-07-15 International Business Machines Corporation Parallel processing system and method using surrogate instructions
US5680597A (en) * 1995-01-26 1997-10-21 International Business Machines Corporation System with flexible local control for modifying same instruction partially in different processor of a SIMD computer system to execute dissimilar sequences of instructions
JPH09106389A (en) 1995-10-12 1997-04-22 Sony Corp Signal processor
US5808690A (en) 1996-01-02 1998-09-15 Integrated Device Technology, Inc. Image generation system, methods and computer program products using distributed processing
US5850489A (en) 1996-01-02 1998-12-15 Integrated Device Technology, Inc. Linear expression evaluator
US5991884A (en) 1996-09-30 1999-11-23 Intel Corporation Method for reducing peak power in dispatching instructions to multiple execution units
US5793655A (en) 1996-10-23 1998-08-11 Zapex Technologies, Inc. Sum of the absolute values generator
US6009505A (en) 1996-12-02 1999-12-28 Compaq Computer Corp. System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot
US5941938A (en) 1996-12-02 1999-08-24 Compaq Computer Corp. System and method for performing an accumulate operation on one or more operands within a partitioned register
US5930403A (en) 1997-01-03 1999-07-27 Zapex Technologies Inc. Method and apparatus for half pixel SAD generation utilizing a FIFO based systolic processor
US6032264A (en) 1997-04-22 2000-02-29 Micron Technology, Inc. Apparatus and method implementing repairs on a memory device
JPH10320573A (en) 1997-05-22 1998-12-04 Sega Enterp Ltd Picture processor, and method for processing picture
US5920515A (en) 1997-09-26 1999-07-06 Advanced Micro Devices, Inc. Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device
US5982395A (en) 1997-12-31 1999-11-09 Cognex Corporation Method and apparatus for parallel addressing of an image processing memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996008778A1 (en) * 1994-09-13 1996-03-21 Lockheed Martin Corporation Parallel data processor
US5724535A (en) * 1994-09-15 1998-03-03 U.S. Philips Corporation Data processing system
EP0726529A2 (en) * 1994-12-29 1996-08-14 International Business Machines Corporation Array processor topology reconfiguration system and method

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AU2001261944A1 (en) 2001-12-03
WO2001090915A2 (en) 2001-11-29
US6728862B1 (en) 2004-04-27

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