WO2001084702A3 - High-speed serial data transceiver systems and related methods - Google Patents

High-speed serial data transceiver systems and related methods Download PDF

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Publication number
WO2001084702A3
WO2001084702A3 PCT/US2001/013637 US0113637W WO0184702A3 WO 2001084702 A3 WO2001084702 A3 WO 2001084702A3 US 0113637 W US0113637 W US 0113637W WO 0184702 A3 WO0184702 A3 WO 0184702A3
Authority
WO
WIPO (PCT)
Prior art keywords
serial data
phase
receiver
sampling
data signal
Prior art date
Application number
PCT/US2001/013637
Other languages
French (fr)
Other versions
WO2001084702A2 (en
Inventor
Aaron Buchwald
Myles Wakayama
Michael Le
Engelen Jurgen Van
Xicheng Jiang
Hui Wang
Howard A Baumer
Avanindra Madisetti
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22743312&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2001084702(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Broadcom Corp filed Critical Broadcom Corp
Priority to AU2001259201A priority Critical patent/AU2001259201A1/en
Priority to EP01932694A priority patent/EP1277304B1/en
Priority to DE60139121T priority patent/DE60139121D1/en
Priority to AT01932694T priority patent/ATE435536T1/en
Publication of WO2001084702A2 publication Critical patent/WO2001084702A2/en
Publication of WO2001084702A3 publication Critical patent/WO2001084702A3/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006Arrangements for removing intersymbol interference
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878Line equalisers; line build-out devices
    • H04L25/03885Line equalisers; line build-out devices adaptive
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H04L7/0274Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit with Costas loop
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L2025/03433Arrangements for removing intersymbol interference characterised by equaliser structure
    • H04L2025/03439Fixed structures
    • H04L2025/03445Time domain
    • H04L2025/03471Tapped delay lines
    • H04L2025/03477Tapped delay lines not time-recursive
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L2025/03592Adaptation methods
    • H04L2025/03598Algorithms
    • H04L2025/03611Iterative algorithms
    • H04L2025/03617Time recursive algorithms
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0016Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0025Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal

Abstract

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.
PCT/US2001/013637 2000-04-28 2001-04-30 High-speed serial data transceiver systems and related methods WO2001084702A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2001259201A AU2001259201A1 (en) 2000-04-28 2001-04-30 High-speed serial data transceiver systems and related methods
EP01932694A EP1277304B1 (en) 2000-04-28 2001-04-30 High-speed serial data transceiver systems and related methods
DE60139121T DE60139121D1 (en) 2000-04-28 2001-04-30 SENDING AND RECEIVING SYSTEMS AND RELATED METHODS FOR SERIAL HIGH-SPEED DATA
AT01932694T ATE435536T1 (en) 2000-04-28 2001-04-30 TRANSMIT AND RECEIVE SYSTEMS AND ASSOCIATED METHODS FOR HIGH SPEED SERIAL DATA

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US20081300P 2000-04-28 2000-04-28
US60/200,813 2000-04-28

Publications (2)

Publication Number Publication Date
WO2001084702A2 WO2001084702A2 (en) 2001-11-08
WO2001084702A3 true WO2001084702A3 (en) 2002-06-06

Family

ID=22743312

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2001/013613 WO2001084724A2 (en) 2000-04-28 2001-04-30 Methods and systems for adaptive receiver equalization
PCT/US2001/013637 WO2001084702A2 (en) 2000-04-28 2001-04-30 High-speed serial data transceiver systems and related methods

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US2001/013613 WO2001084724A2 (en) 2000-04-28 2001-04-30 Methods and systems for adaptive receiver equalization

Country Status (6)

Country Link
US (12) US7012983B2 (en)
EP (3) EP1277316A2 (en)
AT (1) ATE435536T1 (en)
AU (2) AU2001257348A1 (en)
DE (1) DE60139121D1 (en)
WO (2) WO2001084724A2 (en)

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