WO2001084552A3 - Programming of nonvolatile memory cells - Google Patents

Programming of nonvolatile memory cells Download PDF

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Publication number
WO2001084552A3
WO2001084552A3 PCT/IL2001/000399 IL0100399W WO0184552A3 WO 2001084552 A3 WO2001084552 A3 WO 2001084552A3 IL 0100399 W IL0100399 W IL 0100399W WO 0184552 A3 WO0184552 A3 WO 0184552A3
Authority
WO
WIPO (PCT)
Prior art keywords
cell
programming
memory cells
nonvolatile memory
increasing
Prior art date
Application number
PCT/IL2001/000399
Other languages
French (fr)
Other versions
WO2001084552A2 (en
Inventor
Ilan Bloom
Boaz Eitan
Zeev Cohen
David Finzi
Eduardo Maayan
Original Assignee
Saifun Semiconductors Ltd
Ilan Bloom
Boaz Eitan
Zeev Cohen
David Finzi
Eduardo Maayan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Saifun Semiconductors Ltd, Ilan Bloom, Boaz Eitan, Zeev Cohen, David Finzi, Eduardo Maayan filed Critical Saifun Semiconductors Ltd
Priority to AU56618/01A priority Critical patent/AU5661801A/en
Priority to EP01929943A priority patent/EP1287527A4/en
Priority to JP2001581281A priority patent/JP2004503040A/en
Priority to IL15262401A priority patent/IL152624A0/en
Publication of WO2001084552A2 publication Critical patent/WO2001084552A2/en
Publication of WO2001084552A3 publication Critical patent/WO2001084552A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3481—Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Abstract

A method for programming an NROM cell which includes the steps of applying a drain (VD), a source (VS) and a gate voltage (VG) to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.
PCT/IL2001/000399 2000-05-04 2001-05-03 Programming of nonvolatile memory cells WO2001084552A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU56618/01A AU5661801A (en) 2000-05-04 2001-05-03 Programming of nonvolatile memory cells
EP01929943A EP1287527A4 (en) 2000-05-04 2001-05-03 Programming of nonvolatile memory cells
JP2001581281A JP2004503040A (en) 2000-05-04 2001-05-03 Programming non-volatile memory cells
IL15262401A IL152624A0 (en) 2000-05-04 2001-05-03 Programming of nonvolatile memory cells

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/563,923 2000-05-04
US09/563,923 US6396741B1 (en) 2000-05-04 2000-05-04 Programming of nonvolatile memory cells

Publications (2)

Publication Number Publication Date
WO2001084552A2 WO2001084552A2 (en) 2001-11-08
WO2001084552A3 true WO2001084552A3 (en) 2002-02-21

Family

ID=24252440

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2001/000399 WO2001084552A2 (en) 2000-05-04 2001-05-03 Programming of nonvolatile memory cells

Country Status (6)

Country Link
US (2) US6396741B1 (en)
EP (1) EP1287527A4 (en)
JP (1) JP2004503040A (en)
AU (1) AU5661801A (en)
IL (1) IL152624A0 (en)
WO (1) WO2001084552A2 (en)

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