WO2001080549A1

WO2001080549A1 - Arrangement for processing digital video signals in real time

Info

Publication number: WO2001080549A1
Application number: PCT/EP2001/004364
Authority: WO
Inventors: Sieghard Hasenzahl; Rolf Ernst; Peter Rueffer; Kersten Henriss
Original assignee: Koninklijke Philips Electronics N.V.; Philips Corporate Intellectual Property Gmbh
Priority date: 2000-04-17
Filing date: 2001-04-17
Publication date: 2001-10-25
Also published as: EP1417830A1

Abstract

An arrangement for processing digital video signals in real time has at least one field-programmable gate array (1) which can be configured for processing by a program, respectively. The arrangement is preferably provided with a memory consisting of at least one SDRAM (13) into which video data streams to be processed, processed video data streams and video data streams forming intermediate results (6) can be written and from which said video data streams can be read out, in such a way that digital video signals that are delivered to the arrangement are picked up in real time and processed digital video signals are output in real time.

Description

Arrangement for processing digital video signals in real time

The invention relates to an arrangement for processing digital video signals in real time.

Real-time processing is generally required in professional television studios and within television technology equipment. This can consist, for example, of mixing different signals, filtering or influencing the video signals with respect to their characteristic (gradation, black contrast, overall amplitude and the individual components of a color video signal with one another). With the introduction of digital video signals, circuits for processing these signals also became known, but because of the relatively high data rate - for example in the CCIR 601 standard, 270 Mbit / s - they are special "hardware" circuits.

These have the disadvantage that a special circuit must be developed and manufactured for each application, with subsequent changes often not being possible, such as changing the setting range of an actuator or the number of support points of a digital filter.

An improvement in this regard is possible through the use of digital signal processors. Such an application is described, for example, in Maas, Herrmann, Ernst, Rüffer, Hasenzahl, Seitz: "A Processor-Coprocessor Architecture for High End Video Applications" in Proceeding International Conference Acoustics, Speech, and Signal Processing, IEEE pp. 595-598, 1997. Although the hardware described and the software development tools also described there permit largely flexible manufacture of the devices, subsequent changes are also ruled out.

The object of the present invention is to propose an arrangement for real-time processing of digital video signals which is largely neutral on the hardware side and can be configured and reconfigured by appropriate software. This object is achieved according to the invention by at least one field-programmable gate array which can be configured by a program for the respective processing.

A particularly cheap and fast signal processing enables a further development of the arrangement according to the invention in that a memory is formed by at least one SDRAM, into which video data streams to be processed, processed and forming intermediate results can be written and read out from the memory such that the Arrangement supplied digital video signals recorded in real time and processed digital video signals are output in real time. It is preferably provided that a plurality of memory banks are formed in the memory, which are activated overlapping in time for memory accesses. In addition, this development can be designed in such a way that data from a plurality of pixels is processed as a data block and stored in the memory under a start address. This makes optimal use of the available memory bandwidth. The arrangement according to the invention can have two inputs and two

Outputs for digital video signals can be provided. In addition, the arrangement according to the invention can be used for standard television, for example for digital video signals in accordance with CCIR 601, or for high-definition television (HDTV), for example in accordance with the SMPTE 274M standard. One embodiment of the invention is that two independent video

Inputs with 20 bits each in parallel and two synchronous 20 bit parallel video outputs are provided for high-definition television, whereby only 10 bits are required for standard television according to CCIR 601.

Another advantageous embodiment provides that parameters and / or tables for processing the digital video signals can also be stored in the memory. These parameters or tables can represent, for example, non-linear characteristic curves.

In the context of the present invention, the processing of digital video signals in real time does not mean that the video signals are present at the outputs without delay. For example, there may be delays of a few lines or even images if processing so requires - for example if signals from several images are integrated for the purpose of noise reduction.

Another advantageous embodiment of the arrangement according to the invention is that the at least one field-programmable gate array contains a video Interface area, an interface area for the memory, an interface area for a digital signal processor and an interface area for an arithmetic unit also formed by the field programmable gate array. Such a configuration of the field-programmable gate array can be carried out by a program that is stored outside the arrangement, for example on a hard disk. The digital signal processor is used, among other things, to initiate and control the loading of this program. The digital signal processor can also take on administrative tasks in the operation of the arrangement according to the invention. If individual interface areas access the memory several times in succession, it could happen that other interface areas cannot make memory accesses that are necessary for real-time processing. In order to prevent such congestion, a priority management for the access of the interface areas to the memory can be provided in the arrangement according to the invention. For example, the priority of a memory access can be passed on in turn. To load the configuration program, the inventive

Be configured such that an area is further provided as a configuration interface in the field programmable gate array. To enable real-time processing, a much higher clock than the pixel clock of the digital video signals is required within the arrangement according to the invention. In order not to have to couple both clocks with one another, there are buffer memories in the area of the video interface

Equalization of the clocks of the supplied and the output digital video signals and a further clock used for processing the video data streams are provided.

With the buffer memories, which are advantageously realized by FIFOs, the formation of bursts is also possible, that is to say that in each case several pixel data are combined and processed as a data block, for example stored in the memory under a start address. For this purpose, it is advantageous if the memory is also operated with the further clock.

In the arrangement according to the invention it can further be provided that the digital signal processor is operated with a third clock and that the area of the interface for the digital signal processor is buffer memory to compensate for

Differences between the further and the third measure. This means that the digital signal processor can also be operated optimally with regard to its clock frequency.

Exemplary embodiments of the invention are shown in the drawing with reference to several figures and are explained in more detail in the following description. It shows: 1 shows a block diagram of an arrangement according to the invention, and FIG. 2 shows the write and read processes in the SDRAM.

In Fig. 1, single lines are thin and multiple lines thick with correspondingly wide arrows that indicate the direction of data transmission. In the present context, the supplied and processed video signals as well as the processed video signals are referred to as digital video signals. In contrast, the data transmitted with the aid of a data bus 37, which for the most part also represent image information, are referred to as video data or video data streams, in order to emphasize that there is no pixel-by-bit serial data stream here.

1 shows an arrangement according to the invention with a field-programmable gate array 1, which is configured via a permanently installed configuration interface 2 with the aid of a program supplied at 3 in the form of a JT AG program code. For example, a reconfigurable Xilinx Virtex XCV600 or XC4085 field programmable gate array (FPGA) is suitable for the invention. The following areas are formed by the configuration:

- video interface 4,

- Video interface for a digital signal processor (DSP interface) 5,

an interface for the SDRAM 6 and an arithmetic unit 7 with associated interface 8.

Of the interfaces 4, 5, 6 and 8, only FIFO memories 9, 10, 11, 12 are shown, which are important for understanding the timing of the signal processing. Further functions, in particular the control of the signal curve between the interfaces and the further components, are not shown in FIG. 1. An SDRAM 13 and a digital signal processor 14 are connected to the field-programmable gate array 1. Both the SDRAM 13 and the digital signal processor 14 each have their own clock generator 15, 16. Optionally, an arithmetic extension 17 can be connected. This can be a coprocessor or a processing unit formed from a further field programmable gate array. The digital signal processor operates with a memory unit 18 which contains an SRAM and EPROM. The SRAM serves as a working memory, while data for initializing the arrangement after switching on are stored in the EPROM, which is the basis for further configuration of the arrangement with the aid of the data supplied at 3. Further data can be routed via a gate interface 19 and an input / output 20.

For the video signals to be processed, two 20 bit wide inputs 21, 22 are provided with corresponding clock inputs 23, 24. For the processed video signals, two 20 bit wide outputs 25, 26 are also arranged with a common output, to which a clock input 27 is assigned , External synchronization of the two further inputs 28 can also take place.

Between the individual interface areas, bus lines 29, 30, 31 serve as control lines, in particular for the transmission of the information "request, acknowledge, read / write, read FIFO, write FIFO. Further bus lines 32, 33, 34 serve for the transmission of frame, field Finally, video synchronization signals derived within the gate array are distributed via a line 35 in the video interface to the interfaces 5, 6 and 8. However, per se it takes place within the gate array and in the SDRAM the processing according to the clock signal sD _R A _M generated at 15, for which purpose this is fed via lines 36 to the FIFO memories 9 to 12 and the SDRAM interface 6. The clock signal fbsp from the clock generator 16 is also fed to the FIFOs 11 as an input clock as an input clock ,

The bus system 37 connects the outputs of the FIFO memory 9, the inputs of the FIFO memory 10, inputs and outputs of the FIFO memory 11 and the FIFO memory 12 to the data inputs / outputs of the SDRAM 13. It has the Embodiment a width of 64 bits. Other bus lines are shown in Fig. 1 corresponding to that transported by them

Data marked with C for control, A for addresses and D for data.

Fig. 2 illustrates the addressing as well as the write and read process with SDRAM 13. The upper line represents the control data, while the lower line represents the data read or written in each case. For the control data, ACT means activate, NOP no operation or no operation, WR write and RD read. After preparation by ACT and NOP, the write process for a data block consisting of four data words Da, Da + 1, Da + 2 and Da + 3 is started at WR. After the next write command WR, the data block is written from the data words Db to Db + 3. The following control data cause a data block Qc to Qc + 3 to be read, whereupon again a read command comes, which results in the reading of a data block from Qd to Qd + 3. Due to the relatively small number of addressing processes (the address is entered uniformly in the case of a write or read command for the subsequent data block. The SDRAM 13 (FIG. 1) can be operated very effectively. The video signals supplied according to the CCIR 601 standard comprise 10- Bit-

Samples with a frequency of 27 MHz. With the 64-bit SDRAM, nine memory accesses can be carried out within the specified sampling interval with a frequency fs _DRAM ⁼ 40.5 MHz.

For 20-bit samples according to SMPTE 274M, the sampling frequency is 74.25 MHz. If the SDRAM works at the same frequency, then three memory accesses per sample or data word are possible. Since the clocks of the SDRAM, the digital video signals and the digital signal processor are independent of one another through the use of FIFO memories, the number of accesses per data word of the video signals can be increased by a corresponding increase in the clock frequency fs _DRAM . The write / read speed and thus also the overall processing speed can be increased by using DDR SDRAMs (double data rate SDRAMs), in which read and write processes take place on the leading and trailing edges.

Claims

CLAIMS:

1. Arrangement for processing digital video signals in real time, characterized by at least one field-programmable gate array (1) which can be configured by a program for the respective processing.

2. Arrangement according to claim 1, characterized in that a memory (13) is formed by at least one SDRAM, in which pending, processed and intermediate results forming video data streams can be written in and read out from the memory (13) such that the Arrangement supplied digital video signals recorded in real time and processed digital video signals are output in real time.

3. Arrangement according to claim 2, characterized in that a plurality of memory banks are formed in the memory (13), which are activated overlapping in time for memory accesses.

4. Arrangement according to claim 13, characterized in that several data

Pixels are processed as a data block and stored in the memory (13) at a start address.

5. Arrangement according to one of claims 2 to 4, characterized in that in the memory (13) further parameters and / or tables for processing the digital

Video signals can be stored.

6. Arrangement according to one of the preceding claims, characterized in that the at least one field-programmable gate array (1) has a video interface area (4), an interface area (6) for the memory (13), an interface area (5) for one digital signal processor (14) and an interface area (8) for an arithmetic unit (7) also formed by the field programmable gate array (1).

7. Arrangement according to claim 6, characterized in that a

Priority management for the access of the interface areas to the memory (13) is provided.

8. Arrangement according to one of claims 6 or 7, characterized in that in the field programmable gate array (1) an area is further provided as a configuration interface (2).

9. Arrangement according to one of claims 6 to 8, characterized in that in the area of the video interface (4) buffer memory (9, 10) to compensate for the clocks of the supplied and the output digital video signals and one for processing the video Data streams using another clock are provided.

10. The arrangement according to claim 9, characterized in that the memory (13) is operated with the further clock.

11. The arrangement according to claim 10, characterized in that the digital signal processor (14) is operated with a third clock and that the area (5) of the interface for the digital signal processor (14) buffer memory (11) to compensate for differences between the others and the third measure.