WO2001080317A1 - Semiconductor component comprising several semiconductor chips - Google Patents

Abstract

The invention relates to a semiconductor component which in a first embodiment has at least one stack of chips on a carrier substrate, each stack consisting of at least two overlapping semiconductor chips, in particular memory chips. The semiconductor chips of the chip stack are arranged in an offset manner in relation to one another. Each semiconductor chip of a chip stack is connected to the series of conductors of the carrier substrate by electric connections. Alternatively, the invention relates to another semiconductor component, in which at least one chip cluster consisting of at least three semiconductor chips is located on the carrier substrate. In said component, the semiconductor chips are arranged on two overlapping planes in such a way that the semiconductor chips of the first plane overlap those of the other plane. In this embodiment, each semiconductor chip of the chip cluster is also connected electrically to the series of conductors of the carrier substrate.

Description

description

Semiconductor component with several semiconductor chips

The invention relates to a semiconductor component with a plurality of semiconductor chips, in particular with memory chips.

Memory components that are intended for use in a PC, for example, are usually manufactured in the form of so-called modules. Such modules are standardized with regard to their electrical connections, with regard to the spatial arrangement of the electrical connections and with regard to their dimensions. The memory volume of such a module with a predetermined geometric size is therefore dependent on the memory content of each individual semiconductor chip and the number of semiconductor chips arranged on the module. In the case of modules known from the prior art, a multiplicity of identically designed semiconductor chips are arranged next to one another on a substrate. The substrate can consist, for example, of a ceramic and has a conductor track structure which is connected on the one hand to the outer connections of the module and on the other hand establishes an electrical connection to each of the semiconductor chips arranged on the substrate.

There is now a need to further increase the storage volume of such a known module. The object of the present invention is therefore to provide a semiconductor component with a plurality of semiconductor chips in which, with the same geometrical dimensions, a significantly higher memory volume can be achieved compared to a conventional module.

This object is achieved with the features of claim 1 and with the features of claim 8. To achieve this object, the invention proposes a semiconductor component with a carrier substrate provided with conductor tracks and with at least one chip stack, each of at least two semiconductor chips lying one above the other, in particular memory chips, the semiconductor chips of a chip stack being staggered and each semiconductor chip of a chip stack being connected electrically is connected to the conductor tracks of the carrier substrate.

The invention thus enables a semiconductor component, that is to say a memory module, in which the memory contents can be substantially increased due to an inexpensive “chip stack” with only a slight increase in production costs. The increase in the storage volume does not go hand in hand with an increase in the size of the carrier substrate. By stacking several semiconductor chips one above the other, the volume of a module only increases by the volumes of the semiconductor chips arranged one above the other.

Furthermore, the invention alleviates a basic problem when assembling (relatively large) memory chips on a carrier substrate due to a large difference in the thermal expansion coefficients of the components used within a semiconductor component. While silicon has a coefficient of expansion of 3 ppm / K, the thermal coefficient of linear expansion of a carrier substrate made of ceramic or a printed circuit board is between 15 and 18 ppm / K. In particular, when semiconductor chips, each of which are already inserted into a housing, are stacked one above the other, problems can arise due to the different thermal expansion coefficients, which can severely impair the reliability of the semiconductor component. In order to meet the requirements with regard to alternating thermal stresses, various buffer elements or layers would therefore have to be provided in the semiconductor component. This would result in the production of the semiconductor component more complex and expensive. Apart from that, the volume of the semiconductor component would increase significantly. The invention circumvents this problem by stacking a plurality of semiconductor chips directly one above the other. This means that no elements and precautions for thermal adaptation are necessary.

The shifting of semiconductor chips lying one above the other only takes place in one direction. A "slanted chip stack" is created. If several chip stacks are arranged next to one another, the respective semiconductor chips of the next layer of the chip stack are offset by the same distance and in the same direction. This creates "parallel, oblique chip stacks".

Advantageous embodiments of this variant result from the subordinate claims 2 to 7, which are explained in more detail below.

The semiconductor chips advantageously have a bus structure on the side facing away from the substrate

Ladder train structure on. This is preferably implemented using thin-film technology and is essentially used to achieve a logical unbundling of the conductor routing. This makes it possible to dispense with connecting each semiconductor chip of a chip stack directly to the conductor tracks of the carrier substrate by means of a complex connection technology.

Advantageously, respective conductor pattern structures of two semiconductor chips lying one above the other are at least one

Wire connection electrically connected to each other. The conductor track structure is primarily used for "looping through" a signal for semiconductor chips that are not in direct contact with the carrier substrate. The choice to which semiconductor chip signals are to be transmitted is made via a so-called "chip select". A signal is applied to the control lines, which means that each individual half L> M t σι o LΠ o LΠ o Lπ tr φ Φ μ- μ- ω rt

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Accordingly, in an advantageous embodiment, the semiconductor chips have at least on one of their main sides a conductor track structure which forms a bus structure. Thus, not every single semiconductor chip has to be directly electrically connected to the conductor tracks of the carrier substrate. It is sufficient, for example, to electrically connect only two semiconductor chips of a chip assembly directly to the conductor tracks. Due to the bus structure of the conductor track structure, any desired chip can be selectively controlled and data can be exchanged with it.

The conductor track structures of the semiconductor chips on both levels of the chip assembly preferably face one another. Furthermore, it is advantageous to connect the conductor track structures of two overlapping semiconductor chips to one another by means of electrically conductive connecting elements. For example, solder balls (for example solder bumps, polymer bumps) can be provided as connecting elements. It is thus possible to connect the semiconductor chips of the two levels of a chip assembly to one another using the fli-chip method. Both

Solder balls are an inelastic connecting element, which is easy to manufacture cheaply. All connections of the semiconductor chip or of the chip assembly can be produced with a single method step. In the sense of the above-mentioned bus structure, "intertwined" conductor tracks are alternately routed through one level and then through the other. In this case, only one signal is “looped through” via the conductor structure of each semiconductor chip. The state of the active components of a semiconductor chip does not necessarily have to change when a signal is looped through. Two overlapping semiconductor chips can also be directly electrically connected to one another. It is understood here that the active structures of the two semiconductor chips can exchange information with one another. P. 1 1

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see to achieve stability of the entire semiconductor module, it is advantageous to arrange the chip assemblies offset from one another, so that a kind of regular grid is created.

In a further embodiment of the second variant of the invention, a heat distributor is provided on the at least one chip assembly. The elastic wire connections are also advantageously surrounded by a potting compound so that they are protected against mechanical damage.

The rewiring that is necessary in principle for both variants, that is to say the conductor track structure on the semiconductor chips, is advantageously implemented using thin-film technology. The conductor track structures serve primarily to achieve a logical unbundling of the conductor routing.

Further advantages and design variants of the invention are explained in more detail with the aid of the following figures. Show it:

1 shows an example according to the first embodiment of the invention,

FIG. 2 shows a chip assembly that is used in the second variant of the invention,

FIG. 3 shows a first exemplary embodiment according to the second variant of the invention,

FIG. 4 shows a second exemplary embodiment according to the second variant of the invention,

FIG. 5 shows a third exemplary embodiment according to the second variant of the invention, 6 to 8 show an exemplary embodiment of a conductor track structure according to the second variant of the invention,

9a, 9b the arrangement of connecting elements on the conductor structure according to the invention according to FIGS. 6 to 8 and

10a, 10b the arrangement of the connecting elements in a chip assembly according to the invention.

Figure 1 shows an embodiment of the invention according to the first proposed variant. Eight chip stacks 101 are arranged on a carrier substrate 100 on a first main side 102. Of course, more or fewer than the eight chip stacks shown can also be arranged on the carrier substrate 100. In the present exemplary embodiment, a chip stack 101 consists of four semiconductor chips 110, 120, 130, 140. The semiconductor chips 110, 120, 130, 140 are each offset from one another by the same distance. Thus, an area remains on the respective main sides 112, 122, 132, 142 of the semiconductor chips, each of which has a conductor structure 113, 123, 133, 143 that is not visible in cross section. The semiconductor chips or the conductor track structures are connected to one another via wire connections 111, 121, 131, 141. The lowermost semiconductor chip 110 is in this case connected via the wire connection 111 to a conductor track structure on the carrier substrate 100 that cannot be seen in cross section.

The conductor structures on the main rarities of the semiconductor chips take on the function of rewiring. The rewiring is designed in such a way that a bus structure is formed. This means that a plurality of continuous conductor runs extend from the conductor runs on the carrier substrate 100 to the uppermost semiconductor chip 140. This conductor path structure thus leads over all semiconductor chips of a respective chip stack. By controlling certain tax 1 -. 1 0 -. 1 4- ⁾ 1 1

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Φ 0 4-J ISl rH υ Ti 4-1 iH φ Ti _5 SH _s O 4-J -H -H Φ 0 4->, 0 Ti rH = o -H rd 0 tn Φ -H in rd 0 -H 0 r CQ Φ -H = rd Ti, 0 CQ rH 4-J Φ Φ υ M g 4-> M Φ

CQ CQ Φ Φ Φ rH 0 Φ -H Ti _0 0>! 2 in 0 0 = 0 CQ Φ o 4-1 Dl 0 0 CQ 4J 0 ti -H 4H

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Φ rH φ Ti CQ ü 0 4-1 -H Dl ^• Ψ ^• ψ rd Φ -rH u 4-> Φ g in 0 Ti IS! M 0 P iH Φ -0 £ rH

4-> Ti rd P 0 -H td Q g rd rH o 0 4-> Φ CQ _0 0 4J rH ti Φ Φ Φ Φ 4-J υ ti _0 rH O t Pi td CQ PJ OP rH iH rd 4-1 -H CJ CQ ri CQ Φ 0 tn Xi Dl φ CQ 0 -H ri υ φ 0 -H ti o -HO Dl φ SH ti 0 -rH Φ o X PJ IH CJ 0 0 -H Φ td Φ 0 CQ

-rl 0 Φ φ N Ti Φ o Xi 0 0 iH 4-J td Φ rd rH 4-J 0 rd Φ 0 -H cd -H Φ Ti -H rH> Φ

ISl Φ -H Ti 0 in H u • Φ 0 φ rH PJ> _0 Di 0 SH CQ 4-1 Di Φ r- Φ 5 Φ ti Dl tn

Φ tn Ti -H -H ti CQ 4-1 Ti rH Φ Φ υ = 0 φ Φ SH ^" CQ Ti Ti SH CQ -rl rd CQ 0

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-H g Di td 4-> _5 CQ rj iH 0 φ Φ rd 0 Φ CQ 0 Pl EH r-i SH 0 Φ M 0 4-1 4-J CQ

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Φ 4-1 0 -rl H 0 A 0 ü td ti 0 _S Xi -H -. 0 Ti ti Pl CQ rH td CQ -H rH 4J Φ 0 r- {SH _s

Ti -rl Φ Ti Φ CQ rd CQ ISl Φ φ Φ CJ H 4H Φ φ 0 Φ Φ Φ Φ A 0 T5 Φ 0 A Φ

Φ 4-> CQ 4-> Dl -H 0> Dl 0 0 Ti 4-1 ti rd X _s rH A r-i r-i 0 0 -H T) r-i ■ 0 4-J

0 H ti φ Φ iH 0 ti 4-1 <! Φ 0 0 -H rj rd 0 »rd φ u Φ A rd 0 Di 0 rd ü SH φ A 0 0 4-J _0 0 Φ 0 £ -H Φ Φ φ 0 Φ 4J 4-1 -. -. Ά CQ ri t ^< Φ A 0 -rl tu -rl φ

C5 tn r-i _s -H rd = 0 iH Ti Φ Φ ti iH Di Ti Φ r-i tn -H -H 0 tn g td PJ td ^ f ti rH m Φ Di

O 90 0 rd Φ ti MH _0 Ti _0 »rd X -H Φ ti -H Φ rH φ Φ 0 Φ 4-J -H tu 0 rH Φ 0 ti CQ PJ 0

0 tu 0 M 4J Φ = 0 ti -H υ _S 0 Ti rH 0 _0 Φ -H -rl Sä 4- ⁾ 0 Ti CQ, 0 Φ> 0 H Φ CO -rl

O 4-> Φ CQ Dl 4H Φ -H N »rd rH φ = 0 4-1 r-i X -H 0 _0 PJ ü SH 0 _0 0 iH

O -H SH iH o _P CQ CQ Ti 4-> Φ 0 ■ + -1, 0 Φ Ti m ti ti rd in φ Ti υ -H ti _0 rH ^• ψ o υ Φ 0 CQ in

Φ Φ Φ <ψ 0 0 0 Φ CQ rH Φ 0 U 4- ⁾ Φ 0 O Φ 4-J 0 Es ti rd, 0 Φ Φ Φ en o Φ -H = 0 Φ Φ ri Ti Ti H CQ rd rj - H Dl 0 rd CQ N> 4-1 Nl N 0 0 CJ 4-> g N rH rH 4-) P 13 A>

O oo LD H rn

chips, ie thinned semiconductor chips are used. The semiconductor component allows this to be done using known manufacturing methods and technologies.

A production could take place in layers. This means that firstly the semiconductor chips 110 of the first level would be applied to the carrier substrate, for example soldered on. The electrical connection (wire connection 111) between the conductor structure 113 and the (not visible) conductor structure of the carrier substrate 100 is then established. The functionality of the semiconductor chips 110 could then be checked. If this is the case, the second level is applied with the semiconductor chips 120. These are, as shown in Figure 1, applied offset, so that the conductor structure 113 remains recessed. The application can also be done by soldering, gluing or the like. The wire connection 121 is then produced. Since the conductor structure has a bus structure, it is already possible to check the functionality of the semiconductor chips on the second level. If this is the case with all semiconductor chips, the third and fourth levels can be applied. Finally, the heat spreader 104 is applied to the top level of the chip stack 101. The manufacturing process can be carried out in a simple manner by means of a serial bonding process.

FIG. 2 shows a chip assembly as used in a memory module with a high storage volume according to the second variant of the invention. The chip assembly 10 consists of a plurality of semiconductor chips 11 to 17, etc., which are arranged in two superimposed levels. The semiconductor chips 11, 13, 15, 17 ... of the first level each overlap with semiconductor chips 12, 14, 16, ... of the other level. The semiconductor chips of the one and the other plane overlap in such a way that each semiconductor chip - except those which form the outer ends - with two CQ 1 1 1 4H O. 0 4->

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Q Φ -H ti -H A Φ φ CD 0 CQ Φ rd o 0 Φ 0, 0 P 0 td Ti A CQ> 0 13 CQ

• 0 Φ Φ Φ = 0 _5 rH Ti φ 0 -H CM A CQ 0 Φ H A υ rd 4-1 = 0 -H 4-> 0 SH

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A φ _0 Φ A ti 0 Ti ti DM CQ -H 0 -H CQ PJ ISl = 0? ^■ . ti Φ Φ 4-1 A Φ Φ rH LD rd

--ti Ti U -H 0 Φ 0 Φ φ -H φ 0 -rl CQ A 0 4-J -H ti 4-J M A Ti

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0 4-> ti 4-J Φ Φ Dl Ti CQ φ 0 0 ti, 0 -H Φ N A 0 Φ -H 0 υ 0 φ ti -H A CQ ti M -H g 0 0 Dl M> 0 Φ Φ «. = 0 A CQ ti rH Φ Ti <-H td

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W Ti rH CQ -H CQ ti rH 0 Dl 0 Ti -H ti rH -ri rH Φ υ Ti Φ> t ü Φ -. 0 ü 0

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0 CQ rH SH CJ 0 CQ φ CQ ti 0 A Q3 CJ> 4H rH Φ CQ CQ Φ CQ A φ rH 4J A 4-1 0

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Φ A g 4-) CQ ISl A 0 ü CQ Φ Φ, 0 rd rd Φ Φ 0 0 -ri 0 CO -rl M

CM Ti J g £ -H rH SH H TJ rd 0 Dl -H CJ 0 tu Dl 0 0 UH Φ Ti! Φ -. ti φ

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4-J Λ Φ - l Φ A rd 0 φ CQ rH Ti Φ -rl A Ti 0 W td MH 4-J CQ Ti Ti Φ Φ

CQ -H 4-> -rH rH 0 Φ A ti 0 Φ Ti Φ 0 0 -H Ti ü 0 0 φ 0 - rH -. rH Φ -rl CQ rd -H P CJ φ Φ Ti iH 4-J Ti -H rd CM ti 0 td TJ 0 rd Lfl 4-1 Φ ti t-

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90 Φ Φ φ -H Φ Φ Dl rd Ti 0 -H Dl SH -HA _0 4-1 Φ -H rd 4-1 A rd 0 ti Φ rH Ti Ti P 4-> A 0 A CQ 0 φ Φ PM CQ g 0 JJ Φ φ rH P 4-J tu CQ mt ti Φ EH rH

O A iH Ti ti ISl A PJ rd 4-1 l tn φ Φ 4-J CQ 0 A CQ Λ • Φ g A

O rH Φ 4-) • 0 Φ ti υ -H 0 0 0 Φ 0 0 tn 0 0 SH Φ Ti rH • Dl SH rH 0 0 Φ ti Φ g rH td A -H φ rd -H φ rd A -H φ 0 -H 0 -H 0 rd φ Φ -ri ti td φ 0 Φ Φ Φ Φ -HA rH Φ rd tu = 0 g 0 _s 4-> 0 CJ Φ g AP Ti Φ rd A Ti PP 0 tu CQ ISl Ti CO TJ PJ P -H Φ Ti tu

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0 CQ t φ t 0 = 0 0 H rd -rl rH ü CQ Ti N -ri Φ rd 0 0 4-J Φ -rl P 0 4J

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0 Φ X Φ UH xl X! X! Ti φ 0 0 0 ti X! Sä Xl 0 Φ CQ u 4-1 XI -H Ti ü 0 Xl Ti 0

Ti ti X! 0 υ J υ r- Ti -H Ti Φ 4J rH 4-J 0 ^» 0 Φ CQ -H -rl 0 ü 0 -rH CJ Xl

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0 X! Ti CQ Φ 0 0 -H Dl -H φ φ tu CQ CQ »rd φ Sä 4J» 0 -H 0 Φ CJ φ 0 4-> -H

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Φ X! φ X! CQ LT) 13 0 -H »td 0 -H Φ 0 Φ φ 0 4J 0 0 rH -H 4-1 0 ^< 0 PJ o

CQ -H 0 4-J 0 -H φ CQ rH Φ 0 Φ .- Xl rd Ti Ti X! rd Φ 0 Φ -rl -H rd rH 0 H

Φ Ti X! C rd CQ Φ CQ -. 4-> -H CQ 0 Ti X X! ü 0 Φ 0 4-1 0 g 0 0 -H Φ rd

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0 -H rH -H 0 rd 0 Ti rd rH A rd A CQ rd 13 -H Φ 4J φ X! υ ti Ti 0 4H g -H> CQ 0 0 t-- 4-1 Ti Ti Xl Φ Xl -ri 0 A rd Sä 4-1 ti Φ Xl -H -ri XI 0 -H 4-1 0 Φ 0 Φ PM -H Φ XI ti CQ 0 U Ti JA g r- rH 4J ISl CQ φ -H xl • CJ rH φ CQ 0 CQ td m rd 0 0 Φ Ti 0

© XI -. »Rd 0 φ ti 0 LΠ

90 rd CQ -H> Ti J 0 0 ti CQ o 0 tn 0 -ri φ 0 φ XI Φ φ

0 0 4J CQ Φ g Φ Φ tu 4-1 -H Φ Φ 0 4-J CM Φ 0 0 -H 4-> Φ φ 4-J Φ 4-> CQ -n>

© CQ Φ CQ Φ 4J 4-J Dl Pl φ Xl 0 0 0 rH 0 4J> PJ Dl 0 ISl Φ CQ 4-J 0 Ti -ri Dl PJ o 0 Xl 0 0 -H 0 -H »td -ri 0 X! r d Φ ti XI -H 0 -. »Rd Dl 0 4-1 -H X 4J 0 Φ 0 MH -H

Φ Φ φ -rl φ 0 Φ 0 A Φ u -H Sä XI X! = 0 = 0 Φ £ rd o 0 -H φ -rl Φ td -H »O 0 _3 0 0 Xl

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have a larger number of semiconductor chips. The description in the following is again limited to the chip assembly 10, since the chip assembly 30 is constructed identically. The chip assembly 10 has elastic connections 510a and 510b at both ends, each of which electrically connects the outermost semiconductor chips of the lower level to the conductor tracks of the carrier substrate 50. Since the conductor track structures on the main sides of the semiconductor chips are implemented in the form of a bus structure, the elastic wire connection 510a corresponds to the input of the bus system, while the wire connection 510b corresponds to the output of the bus structure.

The elastic wire connections 510a, 510b are in turn surrounded by a casting compound 51 and are thereby mechanically protected.

In the present FIG. 4, there is also no need to provide the mechanical stabilizing semiconductor chip 57 shown in FIG. 3 as a conclusion. This is also not necessary in the present exemplary embodiment, since the lower level of the chip assembly, which is applied to the carrier substrate 50, has one more semiconductor chip than the upper level of the chip assembly 10.

A heat distributor 53 is connected to the upper level of the chip assembly 10, consisting of the semiconductor chips 12, 14, 16, ..., which is connected to the rear sides of the above-mentioned semiconductor chips, for example via a solder layer. The heat spreader 53 can also be glued to the back of the semiconductor chips.

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Wire connection can be produced by means of a bond wire shaped as a spring. Such manufacturing processes are known from the prior art.

LIST OF REFERENCE NUMBERS

10, 20, 30, 40 chip assembly

11 to 19 semiconductor chips

21 to 29 semiconductor chips

31 to 39 semiconductor chips

41 to 49 semiconductor chips

50 carrier substrate

510, 520, 530, 540 (elastic) wire connection

510a, b wire connection

530a, b wire connection

51 potting compound

52 solder layer

53 heat distributors

54 solder layer

55 solder layer or foil (adhesive) or substrate

56 contact pads

57 semiconductor chips

60 conductor line

61 to 68 conductor tracks (CS1 to CS8)

69 ladder train

70a, 70b interruptions (fuses)

71a, 71b connecting elements

72 connecting elements (Solder Bridge)

80 conductor track (memory bus)

81a, b connecting element

100 carrier substrate

101 chips

102, 103 main page

104 heat distributors

105 recess

106 solder layer

110, 120, 130, 140 semiconductor chip 111, 121, 131, 141 wire connection

112, 122, 132, 142 main page

113, 123, 133, 143 trace structure

114, 124, 134, 144 solder layer

Claims

claims

1. Semiconductor component with a carrier substrate (100) provided with conductor tracks and with at least one chip stack (101) each consisting of at least two semiconductor chips (110, 120, 130, 140) one above the other, in particular memory chips, the semiconductor chips (110, 120, 130, 140 ) of a chip stack (101) are arranged offset to one another and each semiconductor chip (110, 120, 130, 140) of a chip stack (101) is connected to the conductor tracks of the carrier substrate (100) via electrical connections (111, 121, 131, 141) ,

2. Semiconductor component according to claim 1, so that the semiconductor chips lying in one plane are offset in two planes arranged adjacent to one another in the same direction and with the same distance from the semiconductor chips lying in the next lower plane.

3. The semiconductor component as claimed in claim 1 or 2, so that the semiconductor chips (110, 120, 130, 140) have a conductor structure (113, 123, 133, 143) forming a bus structure on the side facing away from the substrate (100).

4. Semiconductor component according to one of claims 1 to 3, so that respective conductor structures (113, 123, 133, 143) of semiconductor chips lying one above the other are electrically connected to one another via at least one wire connection (111, 121, 131, 141).

5. Semiconductor component according to one of claims 1 to 4, characterized in that the conductor structure (113, 123, 133, 143) of the semiconductor chip (110) in contact with the carrier substrate (100) with the conductor tracks of the carrier substrate (100) at least a wire connection (111) is electrically connected to one another.

6. Semiconductor component according to one of claims 1 to 5, that a heat distributor (104) is arranged on the uppermost semiconductor chip (140) of a chip stack (101).

7. Semiconductor component according to one of claims 1 to 6, d a d u r c h g e k e n n z e i c h n e t that at least one chip stack (101) is provided on each of the two main sides of the substrate (100).

8. Semiconductor component with a carrier substrate (50) provided with conductor tracks and with at least one chip assembly (10, 20, 30, 40) arranged on the carrier substrate (50) and comprising at least three semiconductor chips (11 ... 19, 21 ... 29, 31 ... 39, 41 ... 49), in which the semiconductor chips are arranged in two superimposed levels, the semiconductor chips (11, 13, 15, ...; 21, 23, 25, ...; 31, 33, 35, ...; 41,

43, 45, ...) with the semiconductor chips (12, 14, ...; 22, 24, ...; 32, 34, ...; 42, 44, ...) of the other level and where each semiconductor chip of the chip assembly (10, 20, 30, 40) is electrically connected to the conductor tracks of the carrier substrate (50).

9. The semiconductor component according to claim 8, so that the semiconductor chips have at least on one of their main sides a conductor structure which forms a bus structure.

10. The semiconductor component as claimed in claim 9, so that the conductor track structures of the semiconductor chips on both levels of the chip assembly (10, 20, 30, 40) face one another.

11. Semiconductor component according to one of claims 8 to 10, characterized in that the conductor track structures of two overlapping semiconductor chips are connected to one another by means of electrically conductive connecting elements (71, 72, 81).

12. Semiconductor component according to one of claims 8 to 11, characterized in that at least one semiconductor chip of the chip assembly (10, 20, 30, 40) is electrically connected to conductor tracks of the carrier substrate (50) via elastic wire connections (510, 520, 530, 540) ,

13. Semiconductor component according to one of claims 8 to 12, characterized in that as the end of that level of the chip assembly (10, 20, 30, 40) that of the outermost semiconductor chip (11, 19; 21, 29, 31, 39; 41, 49 ) overhanging the other level, a semiconductor chip is provided which is adapted in size to the outermost chip of the other level.

14. Semiconductor component according to one of claims 8 to 13, so that at least one chip assembly (10, 20, 30, 40) is provided on each of the two main sides of the carrier substrate (50).

15. The semiconductor component as claimed in one of claims 8 to 14, that at least two chip assemblies (10, 20, 30, 40) are arranged one on top of the other.

16. The semiconductor component as claimed in one of claims 8 to 15, that a heat distributor (53) is provided on the at least one chip assembly (10, 20, 30, 40).

17. A semiconductor device according to one of claims 12 to 16, characterized in that the elastic wire connections (510, 520, 530, 540) are surrounded by a sealing compound (51).