WO2001080312A1 - Pre-application of die attach material to wafer back - Google Patents

Pre-application of die attach material to wafer back Download PDF

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Publication number
WO2001080312A1
WO2001080312A1 PCT/US2000/031800 US0031800W WO0180312A1 WO 2001080312 A1 WO2001080312 A1 WO 2001080312A1 US 0031800 W US0031800 W US 0031800W WO 0180312 A1 WO0180312 A1 WO 0180312A1
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WIPO (PCT)
Prior art keywords
die
attach material
wafer
surface area
die attach
Prior art date
Application number
PCT/US2000/031800
Other languages
French (fr)
Inventor
Sally Y. L. Foong
Kok Khoon Ho
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to KR1020027013922A priority Critical patent/KR20020089492A/en
Priority to JP2001577607A priority patent/JP2003533872A/en
Publication of WO2001080312A1 publication Critical patent/WO2001080312A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
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Definitions

  • TThhee ] present invention relates to die bonding in semiconductor packaging.
  • the present inventio inn hhaass particular applicability in manufacturing stacked die packaging structures.
  • a semiconductor packaging structure known as a "stacked die” package has been developed.
  • a first bare semiconductor chip such as a flash memory device
  • a substrate such as a circuit board or lead frame.
  • a second die such as a DRAM, is likewise bonded to the top surface of the first die, thereby decreasing the required substrate surface area.
  • Both dies are electrically connected to the substrate via wire bonds attached to bonding pads disposed at an exposed peripheral region of each die.
  • the second die is bonded to the top surface of the first die by applying a measured amount of die attach material, typically epoxy paste, to the top surface of the first die.
  • the second die is then placed on the first die, using a conventional diebonder, such that the peripheral bonding pads of the first die are not covered by the second die.
  • the epoxy should not spread beyond the footprint of the second die, thus avoiding contamination of the first die's bonding pads, while ensuring a predetermined die attach material thickness (called "bondline thickness"). Insufficient bondline thickness is associated with decreased reliability of the finished device. Therefore, the epoxy must be accurately placed, and the quantity of epoxy dispensed must be carefully controlled.
  • bondline thickness is typically not consistent from one device to another; i.e., bondline thickness variation is typically greater than 1 mil, resulting in reliability problems.
  • Conventional approaches to solving these problems include increasing the size of the lower die to allow for flow of the epoxy and to avoid fouling the bonding pads; e.g., doubling or tripling the space on the top surface of the first die. However, this is undesirable because it increases the amount of valuable "real estate" occupied by the stacked die assembly.
  • Another approach is to apply the epoxy paste to the back side of the second die before bonding it to the first die.
  • this requires increased handling of the second die, which can easily cause damage to the topside of the second die, resulting in failure of the finished device and/or reliability issues.
  • There exists a need for a methodology for assembling stacked die package structures that prevents die attach material from contaminating the bonding pads, and provides improved control of bondline thickness, thereby improving manufacturing yield and reliability of the finished devices.
  • An advantage of the present invention is a method of die bonding an upper die of a stacked die structure to a lower die that eliminates lower die bonding pad contamination and provides consistent bondline thickness.
  • a method for attaching an upper semiconductor die to a substrate comprising applying a die attach material to a back side of a semiconductor wafer; attaching a sawing tape to the die attach material; sawing through the wafer and the die attach material to form a plurality of dies including the upper die; placing the upper die on the substrate; and curing the die attach material.
  • Another aspect of the present invention is a semiconductor package assembly produced according to the above methodology.
  • Figures 1A-1F schematically illustrate sequential phases of a method in accordance with an embodiment of the present invention.
  • Figure 2A is a side view of a semiconductor package assembly according to an embodiment of the present invention.
  • Figure 2B is a top view of a semiconductor package assembly according to an embodiment of the present invention.
  • die attach material is applied to the upper die of a stacked die package while the upper die is still in wafer form, as by spinning or screening on epoxy in viscous form to the back side of a wafer, or by laminating an epoxy film to the back side of the wafer.
  • the wafer is then placed on sawing tape and sawn into dies, including the upper die.
  • the upper die is thereafter placed on top of the lower die, and the epoxy cured to complete the stacked die assembly.
  • the present invention eliminates the problem of die attach material flowing onto the bonding pads of the lower die.
  • the size of the lower die can be decreased such that when the upper die is attached to the top surface of the lower die, only the bonding area of the lower die is exposed, thereby enabling further miniaturization of the stacked die assembly.
  • bondline thickness between the upper and lower dies can be carefully controlled, improving reliability.
  • a layer of die attach material 110 having a predetermined thickness t such as epoxy having a thickness of about 0.5 mil or less, is applied to back side 100a of a semiconductor wafer 100.
  • Die attach material 110 is preferably applied in the form of a thin film, such as a commercially available B-stage epoxy film available from Hitachi Chemical of Japan or from Sumitomo of Japan.
  • Epoxy film die attach material layer 110 is manually or automatically laminated to back side 100a of wafer 100 with conventional laminating equipment by placing it in contact with back side 100a, then applying heat and pressure, as with a roller, such that it adheres to wafer 100 and air is not trapped between the film and wafer 100. After lamination, die attach material layer 110 is trimmed to the size of wafer 100.
  • die attach material is applied to back side 100a in viscous form by spinning to form layer 110.
  • the spinning method comprises holding wafer 100 in a conventional spinning-type chuck, such as a vacuum chuck used for applying a Pi coating to a wafer top surface in conventional wafer processing techniques.
  • Viscous die attach material such as RP598-3B available from Ablestik Laboratories of Rancho Dominquiez, California, is deposited on the center of back side 100a of wafer 100, and the spinning of the chuck spreads the die attach material to the edges of wafer 100.
  • the spinning speed, the amount of die attach material deposited and the formulation of the die attach material determines the thickness t of of die attach material layer 110.
  • die attach material is applied to back side 100a in viscous form by screening to form layer 110.
  • viscous die attach material such as RP598-3B available from Ablestik Laboratories of Rancho Dominquez, California
  • RP598-3B available from Ablestik Laboratories of Rancho Dominquez, California
  • the screen is placed in contact with back side 100a of wafer 100, and the die attach material is "squeegied" to spread it across back side 100a, resulting in formation of die attach material layer 110 having a predetermined thickness t.
  • conventional sawing tape 120 is attached to die attach material layer 110 using conventional techniques.
  • Wafer 100 and die attach material 110 are then sawn in a conventional manner to form a plurality of dies D each having a surface area a ! (see Fig. ID) such that sawing tape 120 is intact, as shown in Fig. 1C.
  • sawn wafer 100 is brought to a conventional die bonder, where a die D is ejected from sawing tape 120, as by a needle pushing up from below sawing tape 120.
  • Die D is then picked up with a vacuum chuck and placed on a substrate, such as a lower die 130 in a stacked die package (see Fig. IE).
  • lower die 130 preferably has a surface area consisting of a peripheral bonding area 130a and a central surface area 130b about equal to surface area a ! of die D.
  • Die D is preferably placed on lower die 130 such that upper die surface area a] and central surface area 130b are substantially aligned. Thus, when die D is placed on top of lower die 130, only bonding area 130a is exposed.
  • die attach material layer 110 is cured, preferably by heating lower die 130 and die D at the die bonder, as by a heater block, to partially cure die attach material layer 110, then completely curing layer 110 in a conventional curing oven.
  • the present invention by pre-applying die attach material layer 110 to wafer 100 as a film, or by screening or spinning, eliminates the chance of die attach material 110 flowing onto bonding area 130a, thereby improving yield and enabling the size of lower die 130 to be optimized (i.e., minimized).
  • the lower die can be sized such that only the lower die's bonding area 130a is exposed when the upper and lower dies are stacked.
  • a consistent predetermined bondline thickness t is achieved (see Fig. IE), thereby improving reliability of the finished stacked die package.
  • the pre-application of die attach material to the devices in wafer form increases throughput and reduces costs.
  • a semiconductor package assembly produced according to an embodiment of the invention is illustrated in Figs. 2A and 2B.
  • a lower semiconductor die 220 is attached to a substrate 200, such as a printed circuit board, by a first layer of die attach material 210, such as epoxy.
  • An upper semiconductor die 240 is attached to the top surface of lower die 220 by a second layer of epoxy die attach material 230 having a predetermined thickness t.
  • Upper semiconductor die 240 has a surface area a b and lower semiconductor die 220 has a surface area consisting of a peripheral bonding area a 2 and a central surface area a 3 about equal to the upper die surface area a.
  • Upper die 240 is attached to lower die 220 such that upper die surface area a and central surface area a 3 are substantially aligned, and substantially only peripheral bonding area a 2 is exposed. Thus, the size of lower die 220 is minimized.
  • the present invention is applicable to the manufacture of various types of semiconductor packaging structures.
  • the methodology of the present invention can be used for any die bonding application where space and /or bondline thickness are considerations; for example, the present invention can be used to bond the lower die of a stacked die package to the circuit board, as well as to bond the upper die to the lower die.

Abstract

A method is provided for die bonding an upper die of a stacked die structure to a lower die that eliminates lower die bonding pad contamination and provides consistent bondline thickness. Embodiments include applying die attach material to the upper die of a stacked die package while the upper die is still in wafer form, as by spinning or screening on epoxy in viscous form to the back side of a wafer, or by laminating an epoxy film to the back side of the wafer. The wafer is then placed on sawing tape and sawn into dies, including the upper die. The upper die is thereafter placed on top of the lower die, and the epoxy cured. Since viscous die attach material is not deposited on the lower die, die attach material does not flow onto the bonding pads of the lower die. Thus, the size of the lower die can be decreased such that when the upper die is attached to the top surface of the lower die, only the bonding area of the lower die is exposed, thereby enabling miniaturization of the stacked die assembly. Additionally, since the entire die attach area of the upper die is covered with a predetermined amount of die attach material, bondline thickness between the upper and lower dies can be carefully controlled, improving reliability.

Description

PRE- APPLICATION OF DIE ATTACH MATERIAL TO WAFER BACK
FIELD O OFF TTHHEE IINNVVEENNTTIIOONN
TThhee ] present invention relates to die bonding in semiconductor packaging. The present inventio inn hhaass particular applicability in manufacturing stacked die packaging structures.
BACKGROUND ART Due to increasing demands for miniaturization of electronic components, a semiconductor packaging structure known as a "stacked die" package has been developed. In a conventional stacked die package, a first bare semiconductor chip, called a "die", such as a flash memory device, is bonded, as with epoxy adhesive, to a substrate, such as a circuit board or lead frame. A second die, such as a DRAM, is likewise bonded to the top surface of the first die, thereby decreasing the required substrate surface area. Both dies are electrically connected to the substrate via wire bonds attached to bonding pads disposed at an exposed peripheral region of each die.
In conventional stacked die assembly techniques, the second die is bonded to the top surface of the first die by applying a measured amount of die attach material, typically epoxy paste, to the top surface of the first die. The second die is then placed on the first die, using a conventional diebonder, such that the peripheral bonding pads of the first die are not covered by the second die. Ideally, the epoxy should not spread beyond the footprint of the second die, thus avoiding contamination of the first die's bonding pads, while ensuring a predetermined die attach material thickness (called "bondline thickness"). Insufficient bondline thickness is associated with decreased reliability of the finished device. Therefore, the epoxy must be accurately placed, and the quantity of epoxy dispensed must be carefully controlled.
Disadvantageously, due to its viscous nature, despite careful process controls the epoxy paste tends to spread beyond the footprint of the second die onto the bonding pads of the first die, thereby preventing proper wire bonding. Furthermore, bondline thickness is typically not consistent from one device to another; i.e., bondline thickness variation is typically greater than 1 mil, resulting in reliability problems. Conventional approaches to solving these problems include increasing the size of the lower die to allow for flow of the epoxy and to avoid fouling the bonding pads; e.g., doubling or tripling the space on the top surface of the first die. However, this is undesirable because it increases the amount of valuable "real estate" occupied by the stacked die assembly. Another approach is to apply the epoxy paste to the back side of the second die before bonding it to the first die. However, this requires increased handling of the second die, which can easily cause damage to the topside of the second die, resulting in failure of the finished device and/or reliability issues. There exists a need for a methodology for assembling stacked die package structures that prevents die attach material from contaminating the bonding pads, and provides improved control of bondline thickness, thereby improving manufacturing yield and reliability of the finished devices.
SUMMARY OF THE INVENTION
An advantage of the present invention is a method of die bonding an upper die of a stacked die structure to a lower die that eliminates lower die bonding pad contamination and provides consistent bondline thickness.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method for attaching an upper semiconductor die to a substrate, the method comprising applying a die attach material to a back side of a semiconductor wafer; attaching a sawing tape to the die attach material; sawing through the wafer and the die attach material to form a plurality of dies including the upper die; placing the upper die on the substrate; and curing the die attach material.
Another aspect of the present invention is a semiconductor package assembly produced according to the above methodology.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
Reference is made to the attached drawings, wherein elements having the same reference numeral designations represent like elements throughout, and wherein: Figures 1A-1F schematically illustrate sequential phases of a method in accordance with an embodiment of the present invention.
Figure 2A is a side view of a semiconductor package assembly according to an embodiment of the present invention. Figure 2B is a top view of a semiconductor package assembly according to an embodiment of the present invention.
DESCRIPTION OF THE INVENTION
Conventional methods for assembling stacked die packages, which apply viscous die attach material for the upper die on the lower die, require the lower die to be much larger in area than the first die to avoid contamination of the lower die's bonding pads, thereby limiting miniaturization. Moreover, conventional techniques result in insufficient and inconsistent bondline thicknesses, thereby adversely affecting reliability of the finished device. The present invention addresses and solves these problems stemming from conventional manufacturing processes.
According to the methodology of the present invention, die attach material is applied to the upper die of a stacked die package while the upper die is still in wafer form, as by spinning or screening on epoxy in viscous form to the back side of a wafer, or by laminating an epoxy film to the back side of the wafer. The wafer is then placed on sawing tape and sawn into dies, including the upper die. The upper die is thereafter placed on top of the lower die, and the epoxy cured to complete the stacked die assembly. By applying die attach material to the upper die while it is in wafer form, additional handling of the upper die is avoided, and damage to the topside of the upper die prevented. Furthermore, since viscous die attach material is not deposited on the lower die, the present invention eliminates the problem of die attach material flowing onto the bonding pads of the lower die. Thus, the size of the lower die can be decreased such that when the upper die is attached to the top surface of the lower die, only the bonding area of the lower die is exposed, thereby enabling further miniaturization of the stacked die assembly. Moreover, since the entire die attach area of the upper die is covered with a predetermined amount of die attach material, bondline thickness between the upper and lower dies can be carefully controlled, improving reliability.
An embodiment of the methodology of the present invention will now be described with reference to Figs. 1A-1F. As shown in Fig. 1A, a layer of die attach material 110 having a predetermined thickness t, such as epoxy having a thickness of about 0.5 mil or less, is applied to back side 100a of a semiconductor wafer 100. Die attach material 110 is preferably applied in the form of a thin film, such as a commercially available B-stage epoxy film available from Hitachi Chemical of Japan or from Sumitomo of Japan. Epoxy film die attach material layer 110 is manually or automatically laminated to back side 100a of wafer 100 with conventional laminating equipment by placing it in contact with back side 100a, then applying heat and pressure, as with a roller, such that it adheres to wafer 100 and air is not trapped between the film and wafer 100. After lamination, die attach material layer 110 is trimmed to the size of wafer 100.
In an alternative embodiment of the present invention, die attach material is applied to back side 100a in viscous form by spinning to form layer 110. The spinning method comprises holding wafer 100 in a conventional spinning-type chuck, such as a vacuum chuck used for applying a Pi coating to a wafer top surface in conventional wafer processing techniques. Viscous die attach material, such as RP598-3B available from Ablestik Laboratories of Rancho Dominquiez, California, is deposited on the center of back side 100a of wafer 100, and the spinning of the chuck spreads the die attach material to the edges of wafer 100. The spinning speed, the amount of die attach material deposited and the formulation of the die attach material determines the thickness t of of die attach material layer 110.
In another alternative embodiment of the present invention, die attach material is applied to back side 100a in viscous form by screening to form layer 110. In the screening method, viscous die attach material, such as RP598-3B available from Ablestik Laboratories of Rancho Dominquez, California, is placed on a fine mesh screen, such as used in conventional screening techniques. The screen is placed in contact with back side 100a of wafer 100, and the die attach material is "squeegied" to spread it across back side 100a, resulting in formation of die attach material layer 110 having a predetermined thickness t. Referring now to Fig. IB, after die attach material layer 110 is applied, conventional sawing tape 120 is attached to die attach material layer 110 using conventional techniques. Wafer 100 and die attach material 110 are then sawn in a conventional manner to form a plurality of dies D each having a surface area a! (see Fig. ID) such that sawing tape 120 is intact, as shown in Fig. 1C. Next, sawn wafer 100 is brought to a conventional die bonder, where a die D is ejected from sawing tape 120, as by a needle pushing up from below sawing tape 120. Die D is then picked up with a vacuum chuck and placed on a substrate, such as a lower die 130 in a stacked die package (see Fig. IE).
Referring now to Fig. IF, lower die 130 preferably has a surface area consisting of a peripheral bonding area 130a and a central surface area 130b about equal to surface area a! of die D. Die D is preferably placed on lower die 130 such that upper die surface area a] and central surface area 130b are substantially aligned. Thus, when die D is placed on top of lower die 130, only bonding area 130a is exposed. After die D is placed on lower die 130, die attach material layer 110 is cured, preferably by heating lower die 130 and die D at the die bonder, as by a heater block, to partially cure die attach material layer 110, then completely curing layer 110 in a conventional curing oven.
The present invention, by pre-applying die attach material layer 110 to wafer 100 as a film, or by screening or spinning, eliminates the chance of die attach material 110 flowing onto bonding area 130a, thereby improving yield and enabling the size of lower die 130 to be optimized (i.e., minimized). In other words, the lower die can be sized such that only the lower die's bonding area 130a is exposed when the upper and lower dies are stacked. Furthermore, because the thickness of the pre-applied die attach material layer 110 is carefully controlled, a consistent predetermined bondline thickness t is achieved (see Fig. IE), thereby improving reliability of the finished stacked die package. Moreover, the pre-application of die attach material to the devices in wafer form increases throughput and reduces costs.
A semiconductor package assembly produced according to an embodiment of the invention is illustrated in Figs. 2A and 2B. A lower semiconductor die 220 is attached to a substrate 200, such as a printed circuit board, by a first layer of die attach material 210, such as epoxy. An upper semiconductor die 240 is attached to the top surface of lower die 220 by a second layer of epoxy die attach material 230 having a predetermined thickness t. Upper semiconductor die 240 has a surface area ab and lower semiconductor die 220 has a surface area consisting of a peripheral bonding area a2 and a central surface area a3 about equal to the upper die surface area a.\ . Upper die 240 is attached to lower die 220 such that upper die surface area a and central surface area a3 are substantially aligned, and substantially only peripheral bonding area a2 is exposed. Thus, the size of lower die 220 is minimized.
The present invention is applicable to the manufacture of various types of semiconductor packaging structures. The methodology of the present invention can be used for any die bonding application where space and /or bondline thickness are considerations; for example, the present invention can be used to bond the lower die of a stacked die package to the circuit board, as well as to bond the upper die to the lower die.
The present invention can be practiced by employing conventional materials, methodology and equipment. Accordingly, the details of such materials, equipment and methodology are not set forth herein in detail. In the previous descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the present invention. However, it should be recognized that the present invention can be practiced without resorting to the details specifically set forth. In other instances, well known processing structures have not been described in detail, in order not to unnecessarily obscure the present invention.
Only the preferred embodiment of the present invention and but a few examples of its versatility are shown and described in the present disclosure. It is to be understood that the present invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.

Claims

WHAT IS CLAIMED IS:
1. A method for attaching an upper semiconductor die to a substrate, the method comprising: applying a die attach material to a back side of a semiconductor wafer; attaching a sawing tape to the die attach material; sawing through the wafer and the die attach material to form a plurality of dies, the plurality of dies including the upper die; placing the upper die on the substrate; and curing the die attach material.
2. The method of claim 1, wherein the step of applying the die attach material comprises laminating a film comprising die attach material to the back side of the wafer.
3. The method of claim 2, wherein the laminating step comprises: placing the film in contact with the back side of the wafer; heating the wafer; and applying pressure to the film.
4. The method of claim 2, comprising cutting the film at the periphery of the wafer after laminating.
5. The method of claim 1, wherein the step of applying the die attach material comprises spinning the die attach material onto the back side of the wafer.
6. The method of claim 1, wherein the step of applying the die attach material comprises screening the die attach material onto the back side of the wafer.
7. The method of claim 1, wherein the upper die has a surface area, the substrate is a lower semiconductor die having a surface area consisting of a peripheral bonding area and a central surface area about equal to the upper die surface area, the method comprising placing the upper die on the lower die such that the upper die surface area and the central surface area are substantially aligned, and the peripheral bonding area is exposed.
8. The product produced by the method of claim 7.
9. The method of claim 1, wherein the upper die is placed on the substrate at a die bonder, and the curing step comprises: heating the substrate and upper die at the die bonder to partially cure the die attach material; and heating the substrate and upper die in a curing oven to completely cure the die attach material.
10. A semiconductor package assembly comprising: an upper semiconductor die having a surface area; and a lower semiconductor die having a surface area consisting of a peripheral bonding area and a central surface area, the central surface area being about equal to the upper die surface area; wherein the upper die is attached to the lower die such that the upper die surface area and the central surface area are substantially aligned and the peripheral bonding area is exposed.
11. The package assembly of claim 10, further comprising a substrate, wherein the lower die is attached to the substrate.
12. The package assembly of claim 10, comprising a die attach material layer having a predetermined thickness between the upper and lower dies.
PCT/US2000/031800 2000-04-17 2000-11-17 Pre-application of die attach material to wafer back WO2001080312A1 (en)

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