WO2001061935B1 - Cable modem having a programmable media access controller - Google Patents
Cable modem having a programmable media access controllerInfo
- Publication number
- WO2001061935B1 WO2001061935B1 PCT/US2001/005028 US0105028W WO0161935B1 WO 2001061935 B1 WO2001061935 B1 WO 2001061935B1 US 0105028 W US0105028 W US 0105028W WO 0161935 B1 WO0161935 B1 WO 0161935B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- cable
- processors
- cancelled
- media
- processing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/2801—Broadband local area networks
Abstract
A cable modem having a programmable media access controller (MAC). A single cable modem device includes all necessary MAC functions. The invention allows programmable MAC functions to support evolving standards (e.g., DOCSIS) without requiring expensive hardware upgrades. Bifurcated microprocessor architecture, in which first processing circuitry is programmed to implement MAC functionality for processing information flowing to and from cable media interface circuitry, and second embedded processor core or host system processor provides operating system functionality are used. Alternatively, separate processor cores provide MAC functionality for downstream and upstream data paths, respectively. Cable media interface circuitry, and other peripheral circuitry, are coupled to a peripheral bus that is linked by a bridge circuit to a system bus. The processing circuitry MAC is communicatively coupled to the system bus. Centralized DMA control directs data transfer between the peripheral and system buses as determined, at least in part, by the programmable MAC.
Claims
AMENDED CLAIMS
[received by the International Bureau on 12 September 2001 ( 12.09.01 ): original claim 17 amended: original claims 6 and 8-16 cancelled: remaining claims unchanged (3 pages)] . A cable modem having a programmable media access controller, comprising: a system bus; a plurality of processors, each of tbe plurality of processors is communicatively coupled to the system bus, that perform a plurality of processing functions, the plurality of processing functions are partitioned, at least in part, between at least two of the plurality of processors; a peripheral bus that is operable to perform transfer of cable media; a bridge that cornmunicatively couples the system bαs and the peripheral bus; and a peripheral processing device, cormnivnicatively coupled to the peripheral bus, that is operable to perform processing of a selectively off-loaded portion of the cable media.
2. The cable modem of claim 1 , wherein one of the plurahty of processors supports upstream data transfer of cable media received by the cable modem; and at least one other of the plurality of processors supports downstream data transfer of the cable media transmitted by the cable modem.
3. The cable modem of claim 1, wherein one of the plurality of processors is operable to perform at least one of message processing and scheduling.
4. The cable modem of claim 1, wherein the bridge comprises a direct memory access controller that is operable selectively to provide a portion of the cable media to one of the plurahty of processors and to provide the off-loaded portion of the cable media to the peripheral processing device.
5. The cable modem of claim 1, further comprising at least one additional peripheral processing device, communicatively coupled to the peripheral bus, that is operable to perform processing of at least one additional selectively off-loaded portion of the cable media.
6. (Cancelled)
19
7. The cable modem of claim 1, wherein the plurality of processing functions comprises media access control functionality.
8. (Cancelled)
9. (Cancelled)
10. (Cancelled)
11. (Cancelled)
12. (Cancelled)
13. (Cancelled)
14. (Cancelled)
15. (Cancelled)
16. (Cancelled)
17. A method to perform processing within a cable modem, the method comprising: perforating cable media processing using a plurality of processors, the cable media processing is partitioned, at least in part, between at least two of the plurality of processors, wherein each of the plurality of processors is communicatively coupled to a system bus; selectively off-loading a portion of the cable media from at least one of the plurality of processors to a co-processor coramunicauvely coupled to a peripheral bus; and processing the off-loaded portion of the cable media using the co-processor.
20
18. The method of claim 17, wherein the method is performed within an integrated circuit.
19. The method of claim 17, wherein at least one of the plurality of processors comprises embedded code that is substantially operable for media access control functionality.
20. The method of claim 17, further comprising directing upstream and downstream communications of cable media using at least two of the plurality of processors.
21
STATEMENT UNDER ARTICLE 19 (1)
In accordance with PCT Rule 46.5, please substitute enclosed replacement pages 16-18 containing amended claims for original sheets 16-18. No new matter is being added.
22
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01910824A EP1256206A1 (en) | 2000-02-17 | 2001-02-16 | Modem cable avec un controleur d'acces au media programmable |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US18313000P | 2000-02-17 | 2000-02-17 | |
US60/183,130 | 2000-02-17 | ||
US09/785,035 US6816940B2 (en) | 2000-02-17 | 2001-02-16 | Cable modem having a programmable media access controller |
US09/785,035 | 2001-02-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001061935A1 WO2001061935A1 (en) | 2001-08-23 |
WO2001061935B1 true WO2001061935B1 (en) | 2002-01-17 |
Family
ID=26878789
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/005028 WO2001061935A1 (en) | 2000-02-17 | 2001-02-16 | Cable modem having a programmable media access controller |
Country Status (3)
Country | Link |
---|---|
US (1) | US6816940B2 (en) |
EP (1) | EP1256206A1 (en) |
WO (1) | WO2001061935A1 (en) |
Families Citing this family (21)
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IL130796A (en) * | 1999-07-05 | 2003-07-06 | Brightcom Technologies Ltd | Packet processor |
US6651107B1 (en) * | 1999-09-21 | 2003-11-18 | Intel Corporation | Reduced hardware network adapter and communication |
US7110398B2 (en) * | 2001-01-12 | 2006-09-19 | Broadcom Corporation | Packet tag for support of remote network function/packet classification |
US7016376B1 (en) * | 2001-06-26 | 2006-03-21 | Conexant Systems, Inc. | Method and apparatus for scheduling upsteam data packets in a broadband communication system |
US7586914B2 (en) * | 2001-09-27 | 2009-09-08 | Broadcom Corporation | Apparatus and method for hardware creation of a DOCSIS header |
CN100417151C (en) * | 2001-11-30 | 2008-09-03 | 中兴通讯股份有限公司 | Method and apparatus for realizing support circuit business in wireless access system |
US20030140168A1 (en) * | 2002-01-22 | 2003-07-24 | Conexant Systems, Inc. | Assigning addresses to packet-network devices and booting multi-channel devices |
US20040004974A1 (en) * | 2002-07-02 | 2004-01-08 | Harand Gaspar | Method and system for optimizing the design of a network controller |
US7738596B2 (en) * | 2002-09-13 | 2010-06-15 | Broadcom Corporation | High speed data service via satellite modem termination system and satellite modems |
US7171452B1 (en) * | 2002-10-31 | 2007-01-30 | Network Appliance, Inc. | System and method for monitoring cluster partner boot status over a cluster interconnect |
WO2004091104A2 (en) * | 2003-03-31 | 2004-10-21 | Arris International, Inc. | Broadband multi-interface media module |
US8949548B2 (en) * | 2003-09-12 | 2015-02-03 | Broadcom Corporation | System and method of sharing memory by arbitrating through an internal data bus |
US7711948B2 (en) * | 2003-09-30 | 2010-05-04 | Cisco Technology, Inc. | Method and apparatus of communicating security/encryption information to a physical layer transceiver |
US8223775B2 (en) * | 2003-09-30 | 2012-07-17 | Entropic Communications, Inc. | Architecture for a flexible and high-performance gateway cable modem |
US8856401B2 (en) * | 2003-11-25 | 2014-10-07 | Lsi Corporation | Universal controller for peripheral devices in a computing system |
US20060146861A1 (en) * | 2004-12-20 | 2006-07-06 | Ryuji Maeda | System and Method for Communication over a Network with Extended Frequency Range |
US7489641B2 (en) * | 2005-04-25 | 2009-02-10 | Acterna | Data connection quality analysis apparatus and methods |
KR20060133410A (en) * | 2005-06-20 | 2006-12-26 | 엘지전자 주식회사 | Method for managing file database and searching file in multimedia device |
US7428603B2 (en) * | 2005-06-30 | 2008-09-23 | Sigmatel, Inc. | System and method for communicating with memory devices via plurality of state machines and a DMA controller |
DE102006055514A1 (en) * | 2006-05-24 | 2007-11-29 | Robert Bosch Gmbh | Gateway for data transfer between serial buses |
WO2014120113A1 (en) * | 2013-01-29 | 2014-08-07 | Hewlett-Packard Development Company | Assigning processors to memory mapped configuration |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4872197A (en) * | 1986-10-02 | 1989-10-03 | Dti Peripherals, Inc. | Dynamically configurable communications network |
JPH0844649A (en) * | 1994-07-26 | 1996-02-16 | Hitachi Ltd | Data processor |
US5832262A (en) * | 1995-09-14 | 1998-11-03 | Lockheed Martin Corporation | Realtime hardware scheduler utilizing processor message passing and queue management cells |
US5848257A (en) * | 1996-09-20 | 1998-12-08 | Bay Networks, Inc. | Method and apparatus for multitasking in a computer system |
US5761462A (en) * | 1996-12-13 | 1998-06-02 | International Business Machines Corporation | Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data-processing system |
US6421728B1 (en) * | 1997-12-31 | 2002-07-16 | Intel Corporation | Architecture for communicating with and controlling separate upstream and downstream devices |
EP0978788A1 (en) * | 1998-08-04 | 2000-02-09 | Texas Instruments France | Improvements in or relating to direct memory access data transfers |
AU5562400A (en) * | 1999-07-05 | 2001-02-05 | Brightcom Technologies Ltd. | Packet processor |
WO2001006725A2 (en) * | 1999-07-05 | 2001-01-25 | Coresma Ltd. | Process and system for carrying out parallel packet processing |
-
2001
- 2001-02-16 EP EP01910824A patent/EP1256206A1/en not_active Withdrawn
- 2001-02-16 WO PCT/US2001/005028 patent/WO2001061935A1/en active Application Filing
- 2001-02-16 US US09/785,035 patent/US6816940B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6816940B2 (en) | 2004-11-09 |
EP1256206A1 (en) | 2002-11-13 |
US20010039600A1 (en) | 2001-11-08 |
WO2001061935A1 (en) | 2001-08-23 |
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