WO2001053931A3 - Mikroprozessoranordnung und verfahren zum betreiben einer mikroprozessoranordnung - Google Patents

Mikroprozessoranordnung und verfahren zum betreiben einer mikroprozessoranordnung Download PDF

Info

Publication number
WO2001053931A3
WO2001053931A3 PCT/DE2001/000018 DE0100018W WO0153931A3 WO 2001053931 A3 WO2001053931 A3 WO 2001053931A3 DE 0100018 W DE0100018 W DE 0100018W WO 0153931 A3 WO0153931 A3 WO 0153931A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
microprocessor system
cache memory
operating
register
Prior art date
Application number
PCT/DE2001/000018
Other languages
English (en)
French (fr)
Other versions
WO2001053931A2 (de
Inventor
Berndt Gammel
Oliver Kniffler
Holger Sedlak
Original Assignee
Infineon Technologies Ag
Berndt Gammel
Oliver Kniffler
Holger Sedlak
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Berndt Gammel, Oliver Kniffler, Holger Sedlak filed Critical Infineon Technologies Ag
Priority to JP2001554159A priority Critical patent/JP2003521034A/ja
Publication of WO2001053931A2 publication Critical patent/WO2001053931A2/de
Publication of WO2001053931A3 publication Critical patent/WO2001053931A3/de
Priority to US10/197,792 priority patent/US7526655B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography

Abstract

Bei einer Mikroprozessoranordnung werden Daten temporär in einem Cache-Speicher (8) oder einer Registerbank (9) gespeichert. Eine jeweils zugeordnete kryptographische Einheit (81, 82; 91) sorgt für eine Ver-/Entschlüsselung der Daten bei einem Zugriff auf den Cache-Speicher (8) bzw. die Registerbank (9). Das dabei verwendete Schlüsselwort wird verändert, wenn der Cache-speicher (8) bzw. das Register (9) keine gültigen auszulesenden Daten mehr enthält. Dadurch wird eine erhöhte Sicherheit vor einem Ausspähen von Daten und Programmablauf erhalten.
PCT/DE2001/000018 2000-01-18 2001-01-05 Mikroprozessoranordnung und verfahren zum betreiben einer mikroprozessoranordnung WO2001053931A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001554159A JP2003521034A (ja) 2000-01-18 2001-01-05 マイクロプロセッサシステムおよびそれを操作する方法
US10/197,792 US7526655B2 (en) 2000-01-18 2002-07-18 Microprocessor configuration and method for operating a microprocessor configuration

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00100954A EP1118941B1 (de) 2000-01-18 2000-01-18 Mikroprozessoranordnung und Verfahren zum Betreiben einer Mikroprozessoranordnung
EP00100954.7 2000-01-18

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/197,792 Continuation US7526655B2 (en) 2000-01-18 2002-07-18 Microprocessor configuration and method for operating a microprocessor configuration

Publications (2)

Publication Number Publication Date
WO2001053931A2 WO2001053931A2 (de) 2001-07-26
WO2001053931A3 true WO2001053931A3 (de) 2001-12-20

Family

ID=8167654

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/000018 WO2001053931A2 (de) 2000-01-18 2001-01-05 Mikroprozessoranordnung und verfahren zum betreiben einer mikroprozessoranordnung

Country Status (7)

Country Link
US (1) US7526655B2 (de)
EP (1) EP1118941B1 (de)
JP (1) JP2003521034A (de)
CN (1) CN1202478C (de)
AT (1) ATE382897T1 (de)
DE (1) DE50014893D1 (de)
WO (1) WO2001053931A2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10158393A1 (de) * 2001-11-28 2003-06-12 Infineon Technologies Ag Speicher für die Zentraleinheit einer Rechenanlage, Rechenanlage und Verfahren zum Synchronisieren eines Speichers mit dem Hauptspeicher einer Rechenanlage
DE10201442C1 (de) * 2002-01-16 2003-07-31 Infineon Technologies Ag Vorrichtung und Verfahren zum Multiplizieren oder Dividieren eines ersten Operanden mit bzw. durch einen zweiten Operanden
DE10205316B4 (de) * 2002-02-08 2008-01-17 Infineon Technologies Ag Schlüsselmanagementeinrichtung und Verfahren zur verschlüsselten Ablage von digitalen Datenwörtern
FR2840748B1 (fr) * 2002-06-05 2004-08-27 France Telecom Procede et systeme de verification de signatures electroniques et carte a microcircuit pour la mise en oeuvre du procede
US6870873B2 (en) * 2003-05-28 2005-03-22 Systems Spray-Cooled, Inc. Device for improved slag retention in water cooled furnace elements
BR0318492A (pt) * 2003-09-05 2006-09-12 Telecom Italia Spa rede dependente de chave combinatória para criptografia/decifração de dados digitais de entrada, bloco para ser usado para funções criptográficas controladas por chave secreta, método para criptografia/decifração de dados digitais de entrada, dispositivo de processamento de dados, e, dispositivo de multimìdia para armazenar e reproduzir dados digitais
US20050172113A1 (en) * 2004-01-30 2005-08-04 Ati Technologies, Inc. Method and apparatus for basic input output system loading
CA2593441A1 (en) * 2005-02-11 2006-08-17 Universal Data Protection Corporation Method and system for microprocessor data security
US7725719B2 (en) 2005-11-08 2010-05-25 International Business Machines Corporation Method and system for generating ciphertext and message authentication codes utilizing shared hardware
DE102006006057B4 (de) 2006-02-09 2007-12-27 Infineon Technologies Ag Datenverschlüsselungsvorrichtung und Verfahren zum Verschlüsseln von Daten
US7681047B2 (en) 2006-04-18 2010-03-16 International Business Machines Corporation Decryption of data in storage systems
TWI444021B (zh) * 2007-09-17 2014-07-01 Htc Corp 解譯串列傳輸訊號之方法
US8726043B2 (en) * 2009-04-29 2014-05-13 Empire Technology Development Llc Securing backing storage data passed through a network
US8799671B2 (en) * 2009-05-06 2014-08-05 Empire Technology Development Llc Techniques for detecting encrypted data
US8924743B2 (en) * 2009-05-06 2014-12-30 Empire Technology Development Llc Securing data caches through encryption
DE102010045580A1 (de) 2010-09-16 2012-03-22 Infineon Technologies Ag Schaltungsanordnung und Verfahren zum Betreiben einer Schaltungsanordnung
US8858867B2 (en) 2011-02-01 2014-10-14 Superior Machine Co. of South Carolina, Inc. Ladle metallurgy furnace having improved roof
EP2595458A1 (de) 2011-11-16 2013-05-22 Dahwa International Limited Fluoreszenzlampe
CN107590402A (zh) * 2017-09-26 2018-01-16 杭州中天微系统有限公司 一种存储数据加解密装置及方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0583140A1 (de) * 1992-08-11 1994-02-16 International Business Machines Corporation System zur ununterbrochenen Verarbeitung verschlüsselter und unverschlüsselter Daten und Befehle
US5987572A (en) * 1997-09-29 1999-11-16 Intel Corporation Method and apparatus employing a dynamic encryption interface between a processor and a memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866770A (en) * 1986-07-08 1989-09-12 Scientific Atlanta, Inc. Method and apparatus for communication of video, audio, teletext, and data to groups of decoders in a communication system
US4944008A (en) * 1988-02-18 1990-07-24 Motorola, Inc. Electronic keying scheme for locking data
US5757919A (en) * 1996-12-12 1998-05-26 Intel Corporation Cryptographically protected paging subsystem
US6442568B1 (en) * 1998-12-11 2002-08-27 Compaq Computer Corporation Customer information control system application programming interface with transient data functions, in a loosely coupled data processing environment
JP2000276457A (ja) * 1999-03-25 2000-10-06 Mitsubishi Electric Corp データ共有コンピュータシステム及びクライアント

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0583140A1 (de) * 1992-08-11 1994-02-16 International Business Machines Corporation System zur ununterbrochenen Verarbeitung verschlüsselter und unverschlüsselter Daten und Befehle
US5987572A (en) * 1997-09-29 1999-11-16 Intel Corporation Method and apparatus employing a dynamic encryption interface between a processor and a memory

Also Published As

Publication number Publication date
ATE382897T1 (de) 2008-01-15
US7526655B2 (en) 2009-04-28
CN1202478C (zh) 2005-05-18
US20030005314A1 (en) 2003-01-02
CN1395702A (zh) 2003-02-05
JP2003521034A (ja) 2003-07-08
EP1118941A1 (de) 2001-07-25
DE50014893D1 (de) 2008-02-14
EP1118941B1 (de) 2008-01-02
WO2001053931A2 (de) 2001-07-26

Similar Documents

Publication Publication Date Title
WO2001053931A3 (de) Mikroprozessoranordnung und verfahren zum betreiben einer mikroprozessoranordnung
EP1298518A3 (de) Mikroprozessor mit verbesserten Taskverwaltungs- und Tabellenverwaltungsvorrichtungen
GB2387937B (en) Secure cpu and memory management unit with cryptographic extensions
WO2003023578A3 (en) Using data stored in a destructive-read memory
US20100017625A1 (en) Architecure, system, and method for operating on encrypted and/or hidden information
EP0114522A3 (de) Festwertspeichersicherungseinrichtung
DK0536286T3 (da) Sikkerhedssystem med fordelt database
BR0211093A (pt) Sistema e método para efetuar o cache de chave de mensagem segura em um dispositivo de comunicação móvel
CN100397284C (zh) 具有非易失存储器模块的电路装置以及对非易失存储器模块中的数据进行加密/解密的方法
CA2028751A1 (en) Device for controlling communication between electronic information cards and host computer to be kept in secret
WO2003038574A3 (en) An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment
EP0471538A2 (de) Datensicherheitseinrichtung
WO2006118667A3 (en) Prefetching across a page boundary
CA2469682A1 (en) Cache operation with non-cache memory
EE200400053A (et) Meetod ja süsteem andmete töötlemiseks elektroonilises seadmes, elektrooniline seade ja töötlusplokk
BR9808167A (pt) Dispositivo e sistema de processamento de dados eletrônicos
KR960015239A (ko) 정보 처리 장치 및 이에 조합된 장치에 있어서 보호된 저장 영역의 로딩 방법
ES2069553T3 (es) Terminal controlado por soporte de datos en un sistema de intercambio de datos.
ES2169120T3 (es) Tarjeta de memoria segura con control de acceso de seguridad controlado por programa.
WO2003001350A3 (en) Security system and software to prevent unauthorized use of a computing device
JP2005515542A (ja) 対応するコンピュータプログラム及び対応するコンピュータにより読み出し可能な記憶媒体と共にコントローラアーキテクチャにおけるｎｖメモリに書き込むための装置及び方法
TW344050B (en) Data cache having data storage and tag/hit/miss logic in separate clock domains
JP2004525470A (ja) 中央処理装置とメモリとの間でのデータ送信を保護する方法及び装置
WO2002057906A3 (de) Mikroprozessorschaltung_mit hilfsregister
ATE378679T1 (de) Computerlesbares medium mit mikroprozessor zur lesesteuerung und computeranordnung zur kommunikation mit einem derartigen medium

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): BR CN IN JP KR MX RU UA US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): BR CN IN JP KR MX RU UA US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

ENP Entry into the national phase

Ref country code: JP

Ref document number: 2001 554159

Kind code of ref document: A

Format of ref document f/p: F

WWE Wipo information: entry into national phase

Ref document number: 018038042

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 10197792

Country of ref document: US

122 Ep: pct application non-entry in european phase