WO2001048819A3 - Interconnect structure and method of fabrication therefor - Google Patents

Interconnect structure and method of fabrication therefor Download PDF

Info

Publication number
WO2001048819A3
WO2001048819A3 PCT/US2000/035483 US0035483W WO0148819A3 WO 2001048819 A3 WO2001048819 A3 WO 2001048819A3 US 0035483 W US0035483 W US 0035483W WO 0148819 A3 WO0148819 A3 WO 0148819A3
Authority
WO
WIPO (PCT)
Prior art keywords
hole
interconnect structure
pth
dielectric layers
core material
Prior art date
Application number
PCT/US2000/035483
Other languages
French (fr)
Other versions
WO2001048819A2 (en
Inventor
Bob Sankman
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to AU24618/01A priority Critical patent/AU2461801A/en
Publication of WO2001048819A2 publication Critical patent/WO2001048819A2/en
Publication of WO2001048819A3 publication Critical patent/WO2001048819A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An interconnect structure for microelectronic devices includes a first plated through hole (PTH) via formed through a core material, and a second PTH via concentrically located inside first PTH via, but electrically isolated from the first PTH via. A method of producing the interconnect structure includes forming a first hole through a core material layer, then forming a first conductive layer on sidewalls of the first hole, and on upper and lower surfaces of the core material layer. The first hole is substantially filled with non-conductive material, and dielectric layers are formed on substantially horizontal portions of the first conductive layer, and on top and bottom surfaces of the non-conductive material. A second hole, having a smaller diameter than the diameter of the first hole, is formed through the dielectric layers and the non-conductive material in concentric relationship to the first hole. A second conductive layer is then formed on the sidewalls of the second hole, and on upper and lower surfaces of the dielectric layers.
PCT/US2000/035483 1999-12-28 2000-12-28 Interconnect structure and method of fabrication therefor WO2001048819A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU24618/01A AU2461801A (en) 1999-12-28 2000-12-28 Interconnect structure and method of fabrication therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47327299A 1999-12-28 1999-12-28
US09/473,272 1999-12-28

Publications (2)

Publication Number Publication Date
WO2001048819A2 WO2001048819A2 (en) 2001-07-05
WO2001048819A3 true WO2001048819A3 (en) 2002-03-07

Family

ID=23878876

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/035483 WO2001048819A2 (en) 1999-12-28 2000-12-28 Interconnect structure and method of fabrication therefor

Country Status (2)

Country Link
AU (1) AU2461801A (en)
WO (1) WO2001048819A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7102892B2 (en) 2000-03-13 2006-09-05 Legacy Electronics, Inc. Modular integrated circuit chip carrier
KR100980356B1 (en) * 2002-02-26 2010-09-06 레가시 일렉트로닉스, 인크. Modular integrated circuit chip carrier
CN104519658B (en) * 2013-09-30 2017-09-29 北大方正集团有限公司 The preparation method and circuit board of a kind of circuit board skip floor blind hole
CN106653318B (en) * 2017-02-28 2019-06-18 华为技术有限公司 Inductance component and crisscross parallel DC converter

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4675788A (en) * 1984-07-17 1987-06-23 Schroff Gesellschaft Mit Beschrankter Haftung Multi-layer circuit board
JPH0294693A (en) * 1988-09-30 1990-04-05 Nec Corp Printed wiring board having coaxial through-hole
US5257452A (en) * 1991-05-27 1993-11-02 Hitachi, Ltd. Methods of recovering a multi-layer printed circuit board
EP0591887A2 (en) * 1992-10-09 1994-04-13 International Business Machines Corporation Printed wiring board
US5421083A (en) * 1994-04-01 1995-06-06 Motorola, Inc. Method of manufacturing a circuit carrying substrate having coaxial via holes
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
US5949030A (en) * 1997-11-14 1999-09-07 International Business Machines Corporation Vias and method for making the same in organic board and chip carriers

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4675788A (en) * 1984-07-17 1987-06-23 Schroff Gesellschaft Mit Beschrankter Haftung Multi-layer circuit board
JPH0294693A (en) * 1988-09-30 1990-04-05 Nec Corp Printed wiring board having coaxial through-hole
US5257452A (en) * 1991-05-27 1993-11-02 Hitachi, Ltd. Methods of recovering a multi-layer printed circuit board
EP0591887A2 (en) * 1992-10-09 1994-04-13 International Business Machines Corporation Printed wiring board
US5421083A (en) * 1994-04-01 1995-06-06 Motorola, Inc. Method of manufacturing a circuit carrying substrate having coaxial via holes
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
US5949030A (en) * 1997-11-14 1999-09-07 International Business Machines Corporation Vias and method for making the same in organic board and chip carriers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 014, no. 292 (E - 0944) 25 June 1990 (1990-06-25) *

Also Published As

Publication number Publication date
WO2001048819A2 (en) 2001-07-05
AU2461801A (en) 2001-07-09

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